clk: tegra: Make vic03 a child of pll_c3

Message ID 20180611081853.31474-1-thierry.reding@gmail.com
State New
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Series
  • clk: tegra: Make vic03 a child of pll_c3
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Commit Message

Thierry Reding June 11, 2018, 8:18 a.m.
From: Thierry Reding <treding@nvidia.com>

By default, the vic03 clock is a child of pll_m but that runs at 924 MHz
which is too fast for VIC. Make vic03 a child of pll_c3 by default so it
will run at a supported frequency.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/clk/tegra/clk-tegra124.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Thierry Reding June 11, 2018, 8:22 a.m. | #1
On Mon, Jun 11, 2018 at 10:18:53AM +0200, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> By default, the vic03 clock is a child of pll_m but that runs at 924 MHz
> which is too fast for VIC. Make vic03 a child of pll_c3 by default so it
> will run at a supported frequency.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  drivers/clk/tegra/clk-tegra124.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
> index 0c69c7970950..f5048f82c0b9 100644
> --- a/drivers/clk/tegra/clk-tegra124.c
> +++ b/drivers/clk/tegra/clk-tegra124.c
> @@ -1290,6 +1290,7 @@ static struct tegra_clk_init_table common_init_table[] __initdata = {
>  	{ TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1 },
>  	{ TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1 },
>  	{ TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0 },
> +	{ TEGRA124_CLK_VIC03, TEGRA124_CLK_PLL_C3, 0, 0 },
>  	/* must be the last entry */
>  	{ TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
>  };

Adding Peter for visibility.

Thierry
Peter De Schrijver June 12, 2018, 3:40 p.m. | #2
On Mon, Jun 11, 2018 at 10:22:44AM +0200, Thierry Reding wrote:
> On Mon, Jun 11, 2018 at 10:18:53AM +0200, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> > 
> > By default, the vic03 clock is a child of pll_m but that runs at 924 MHz
> > which is too fast for VIC. Make vic03 a child of pll_c3 by default so it
> > will run at a supported frequency.
> > 
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> >  drivers/clk/tegra/clk-tegra124.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
> > index 0c69c7970950..f5048f82c0b9 100644
> > --- a/drivers/clk/tegra/clk-tegra124.c
> > +++ b/drivers/clk/tegra/clk-tegra124.c
> > @@ -1290,6 +1290,7 @@ static struct tegra_clk_init_table common_init_table[] __initdata = {
> >  	{ TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1 },
> >  	{ TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1 },
> >  	{ TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0 },
> > +	{ TEGRA124_CLK_VIC03, TEGRA124_CLK_PLL_C3, 0, 0 },
> >  	/* must be the last entry */
> >  	{ TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
> >  };
> 
> Adding Peter for visibility.

I think we should consider using the Assigned clock parents and rate feature
of the DT clock binding.

Peter.
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Thierry Reding June 13, 2018, 1:17 p.m. | #3
On Tue, Jun 12, 2018 at 06:40:25PM +0300, Peter De Schrijver wrote:
> On Mon, Jun 11, 2018 at 10:22:44AM +0200, Thierry Reding wrote:
> > On Mon, Jun 11, 2018 at 10:18:53AM +0200, Thierry Reding wrote:
> > > From: Thierry Reding <treding@nvidia.com>
> > > 
> > > By default, the vic03 clock is a child of pll_m but that runs at 924 MHz
> > > which is too fast for VIC. Make vic03 a child of pll_c3 by default so it
> > > will run at a supported frequency.
> > > 
> > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > > ---
> > >  drivers/clk/tegra/clk-tegra124.c | 1 +
> > >  1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
> > > index 0c69c7970950..f5048f82c0b9 100644
> > > --- a/drivers/clk/tegra/clk-tegra124.c
> > > +++ b/drivers/clk/tegra/clk-tegra124.c
> > > @@ -1290,6 +1290,7 @@ static struct tegra_clk_init_table common_init_table[] __initdata = {
> > >  	{ TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1 },
> > >  	{ TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1 },
> > >  	{ TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0 },
> > > +	{ TEGRA124_CLK_VIC03, TEGRA124_CLK_PLL_C3, 0, 0 },
> > >  	/* must be the last entry */
> > >  	{ TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
> > >  };
> > 
> > Adding Peter for visibility.
> 
> I think we should consider using the Assigned clock parents and rate feature
> of the DT clock binding.

I'm sure we could do that, but it'd also be completely inconsistent with
what we've done so far. These init tables effectively do the same thing
as the assigned parents and rate bindings, only they predate them and we
have done it this way essentially forever.

I think there's some benefit in moving to the new bindings, but perhaps
it'd make more sense to do it for Tegra186 and later because we don't
have any of these initialization tables there yet and we don't even have
a custom driver like this.

Thierry

Patch

diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 0c69c7970950..f5048f82c0b9 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1290,6 +1290,7 @@  static struct tegra_clk_init_table common_init_table[] __initdata = {
 	{ TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1 },
 	{ TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1 },
 	{ TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0 },
+	{ TEGRA124_CLK_VIC03, TEGRA124_CLK_PLL_C3, 0, 0 },
 	/* must be the last entry */
 	{ TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
 };