[v2,4/4] dt-bindings: pwm: fsl-ftm: Add compatible string for i.MX8QM

Message ID 20180608192237.11063-4-shenwei.wang@nxp.com
State Accepted
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Series
  • [v2,1/4] pwm: fsl-ftm: Added a dedicated IP interface clock
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Commit Message

Shenwei Wang June 8, 2018, 7:22 p.m.
i.MX8QM integrates a new version of FTM IP block. It adds eight
PWM enable bits in FTM_SC register.
Add a new compatible string of "fsl,imx8qm-ftm-pwm" for i.MX8QM
to differentiate it from the previous SoCs.

Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
---
 Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

Patch

diff --git a/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt b/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt
index 3899d6a..576ad00 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt
@@ -16,7 +16,10 @@  modes in device tree.
 
 
 Required properties:
-- compatible: Should be "fsl,vf610-ftm-pwm".
+- compatible : should be "fsl,<soc>-ftm-pwm" and one of the following
+   compatible strings:
+  - "fsl,vf610-ftm-pwm" for PWM compatible with the one integrated on VF610
+  - "fsl,imx8qm-ftm-pwm" for PWM compatible with the one integrated on i.MX8QM
 - reg: Physical base address and length of the controller's registers
 - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of
   the cells format.