From patchwork Wed Jun 6 05:35:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 925742 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 410yFZ6HWVzB3sg for ; Wed, 6 Jun 2018 15:40:50 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 410yFZ4XlSzF2Z9 for ; Wed, 6 Jun 2018 15:40:50 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=hegdevasant@linux.vnet.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 410y8g4JsbzF30y for ; Wed, 6 Jun 2018 15:36:35 +1000 (AEST) Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w565YQFe103752 for ; Wed, 6 Jun 2018 01:36:33 -0400 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 2je9cj0hqq-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 06 Jun 2018 01:36:33 -0400 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 6 Jun 2018 06:36:28 +0100 Received: from d06av24.portsmouth.uk.ibm.com (mk.ibm.com [9.149.105.60]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w565aSWa31195136 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 6 Jun 2018 05:36:28 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A51AA42041; Wed, 6 Jun 2018 06:26:49 +0100 (BST) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 835CC42042; Wed, 6 Jun 2018 06:26:48 +0100 (BST) Received: from hegdevasant.in.ibm.com (unknown [9.199.176.210]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 6 Jun 2018 06:26:48 +0100 (BST) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 6 Jun 2018 11:05:35 +0530 X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180606053535.8855-1-hegdevasant@linux.vnet.ibm.com> References: <20180606053535.8855-1-hegdevasant@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18060605-0008-0000-0000-000002449B62 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18060605-0009-0000-0000-000021AAA3C8 Message-Id: <20180606053535.8855-19-hegdevasant@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-06-06_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1805220000 definitions=main-1806060064 Subject: [Skiboot] [PATCH v3 18/18] mbox: Reset bmc mbox in MPIPL path X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" During boot SBE and early hostboot does not use MBOX protocol to get image from PNOR. Instead it expects PNOR TOC and Hostboot Boot Boot Loader to be availabe at particular address in LPC bus. mbox daemon in BMC side takes care of this during normal boot. Once boot is complete mbox daemon swiches to normal mode. During normal reboot, BMC side mbox daemon gets notification and takes care of loading PNOR TOC and HBBL to LPC bus again. In MPIPL path, OPAL call SBE S0/S1 interrupt to initiate MPIPL. BMC will not be aware of this. But SBE expects PNOR TOC and HBBL to be available in LPC bus at predefined address. Hence call MBOX Reset from OPAL in assert path. Note that this is workaround to get mbox working for now. Long term solution is to use a bit in the Host Status byte of the mbox protocol's memory layout to indicate to mboxd that the host is preparing for reboot. We will implement once BMC side implementation is complete. CC: Andrew Jeffery Signed-off-by: Vasant Hegde Reviewed-by: Andrew Jeffery --- core/flash.c | 8 ++++++++ hw/sbe-p9.c | 3 +++ include/skiboot.h | 1 + libflash/blocklevel.h | 1 + libflash/mbox-flash.c | 22 ++++++++++++++++++++++ 5 files changed, 35 insertions(+) diff --git a/core/flash.c b/core/flash.c index e3be57613..474f36f0f 100644 --- a/core/flash.c +++ b/core/flash.c @@ -76,6 +76,14 @@ void flash_release(void) unlock(&flash_lock); } +void flash_reset(void) +{ + struct blocklevel_device *bl = system_flash->bl; + + if (dt_find_compatible_node(dt_root, NULL, "mbox")) + bl->reset(bl); +} + static int flash_nvram_info(uint32_t *total_size) { int rc; diff --git a/hw/sbe-p9.c b/hw/sbe-p9.c index 627ef428a..c6df40fa2 100644 --- a/hw/sbe-p9.c +++ b/hw/sbe-p9.c @@ -941,6 +941,9 @@ void __attribute__((noreturn)) p9_sbe_terminate(const char *msg) int rc, waited = 0; struct dt_node *xn; + /* Reset BMC MBOX driver */ + flash_reset(); + dt_for_each_compatible(dt_root, xn, "ibm,xscom") { chip_id = dt_get_chip_id(xn); diff --git a/include/skiboot.h b/include/skiboot.h index b4bdf3779..badbd9ebf 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -255,6 +255,7 @@ extern int flash_start_preload_resource(enum resource_id id, uint32_t subid, extern int flash_resource_loaded(enum resource_id id, uint32_t idx); extern bool flash_reserve(void); extern void flash_release(void); +extern void flash_reset(void); #define FLASH_SUBPART_ALIGNMENT 0x1000 #define FLASH_SUBPART_HEADER_SIZE FLASH_SUBPART_ALIGNMENT extern int flash_subpart_info(void *part_header, uint32_t header_len, diff --git a/libflash/blocklevel.h b/libflash/blocklevel.h index ba42c83d0..e11dbfbfb 100644 --- a/libflash/blocklevel.h +++ b/libflash/blocklevel.h @@ -47,6 +47,7 @@ struct blocklevel_device { int (*erase)(struct blocklevel_device *bl, uint64_t pos, uint64_t len); int (*get_info)(struct blocklevel_device *bl, const char **name, uint64_t *total_size, uint32_t *erase_granule); + int (*reset)(struct blocklevel_device *bl); /* * Keep the erase mask so that blocklevel_erase() can do sanity checking diff --git a/libflash/mbox-flash.c b/libflash/mbox-flash.c index 6742d215c..dd5ac2f88 100644 --- a/libflash/mbox-flash.c +++ b/libflash/mbox-flash.c @@ -818,6 +818,27 @@ static int mbox_flash_read(struct blocklevel_device *bl, uint64_t pos, return rc; } +static int mbox_flash_reset(struct blocklevel_device *bl) +{ + int rc; + struct mbox_flash_data *mbox_flash; + struct bmc_mbox_msg msg = MSG_CREATE(MBOX_C_RESET_STATE); + + mbox_flash = container_of(bl, struct mbox_flash_data, bl); + + rc = msg_send(mbox_flash, &msg, mbox_flash->timeout); + if (rc) { + prlog(PR_ERR, "Failed to enqueue/send BMC MBOX RESET msg\n"); + return rc; + } + if (wait_for_bmc(mbox_flash, mbox_flash->timeout)) { + prlog(PR_ERR, "Error waiting for BMC\n"); + return rc; + } + + return OPAL_SUCCESS; +} + static int mbox_flash_get_info(struct blocklevel_device *bl, const char **name, uint64_t *total_size, uint32_t *erase_granule) { @@ -1147,6 +1168,7 @@ int mbox_flash_init(struct blocklevel_device **bl) mbox_flash->bl.write = &mbox_flash_write; mbox_flash->bl.erase = &mbox_flash_erase_v2; mbox_flash->bl.get_info = &mbox_flash_get_info; + mbox_flash->bl.reset = &mbox_flash_reset; if (bmc_mbox_get_attn_reg() & MBOX_ATTN_BMC_REBOOT) rc = handle_reboot(mbox_flash);