| Message ID | 20180604214819.11917-1-dgilmore@redhat.com |
|---|---|
| State | Awaiting Upstream |
| Delegated to: | Stefan Roese |
| Headers | show |
| Series | [U-Boot] arm: mvebu: Add Helios4 Armada 38x initial support | expand |
Hi Dennis, On Tue, Jun 5, 2018 at 9:53 AM <dgilmore@redhat.com> wrote: > > From: Dennis Gilmore <dennis@ausil.us> > > The helios4 is built on the SolidRun Armada 38x SOM. > The port os based on the ClearFog board, using information from > https://github.com/helios-4/u-boot-marvell as well as dtb input > from https://github.com/helios-4/linux-marvell > > Signed-off-by: Dennis Gilmore <dennis@ausil.us> > Signed-off-by: Dennis Gilmore <dgilmore@redhat.com> Some comments below, nothing major Reviewed-by: Chris Packham <judge.packham@gmail.com> > --- > changes since RFC > add armada-38x-solidrun-microsom.dtsi minus buffer-memory nodes from linux kernel > fix up maintainers file > use correct switch in README file > add SPDX header to kwbimage.cfg and dts file > Port to DM_I2C > > I have not ported to generic gpio yet, not had time to investigate and none of the > marvell boards that already exist even thoughse with some generic gpio have ported > the functions in helios4.c > --- > arch/arm/dts/Makefile | 1 + > arch/arm/dts/armada-388-helios4.dts | 308 ++++++++++++++++++ > .../arm/dts/armada-38x-solidrun-microsom.dtsi | 100 ++++++ > arch/arm/mach-mvebu/Kconfig | 7 + > board/solidrun/helios4/MAINTAINERS | 6 + > board/solidrun/helios4/Makefile | 5 + > board/solidrun/helios4/README | 46 +++ > board/solidrun/helios4/helios4.c | 172 ++++++++++ > board/solidrun/helios4/kwbimage.cfg | 13 + > configs/helios4_defconfig | 58 ++++ > include/configs/helios4.h | 178 ++++++++++ > 11 files changed, 894 insertions(+) > create mode 100644 arch/arm/dts/armada-388-helios4.dts > create mode 100644 arch/arm/dts/armada-38x-solidrun-microsom.dtsi > create mode 100644 board/solidrun/helios4/MAINTAINERS > create mode 100644 board/solidrun/helios4/Makefile > create mode 100644 board/solidrun/helios4/README > create mode 100644 board/solidrun/helios4/helios4.c > create mode 100644 board/solidrun/helios4/kwbimage.cfg > create mode 100644 configs/helios4_defconfig > create mode 100644 include/configs/helios4.h > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index a0349a8975..a18f4bbf7b 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -91,6 +91,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ > armada-375-db.dtb \ > armada-388-clearfog.dtb \ > armada-388-gp.dtb \ > + armada-388-helios4.dtb \ > armada-385-amc.dtb \ > armada-7040-db.dtb \ > armada-7040-db-nand.dtb \ > diff --git a/arch/arm/dts/armada-388-helios4.dts b/arch/arm/dts/armada-388-helios4.dts > new file mode 100644 > index 0000000000..3223e4d71f > --- /dev/null > +++ b/arch/arm/dts/armada-388-helios4.dts > @@ -0,0 +1,308 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > + > +/dts-v1/; > +#include "armada-388.dtsi" > +#include "armada-38x-solidrun-microsom.dtsi" > + > +/ { > + model = "Helios4"; > + compatible = "solidrun,helios4", "marvell,armada388", > + "marvell,armada385", "marvell,armada380"; > + > + memory { > + device_type = "memory"; > + reg = <0x00000000 0x80000000>; /* 2 GB */ > + }; > + > + aliases { > + /* So that mvebu u-boot can update the MAC addresses */ > + ethernet1 = ð0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + reg_12v: regulator-12v { > + compatible = "regulator-fixed"; > + regulator-name = "power_brick_12V"; > + regulator-min-microvolt = <12000000>; > + regulator-max-microvolt = <12000000>; > + regulator-always-on; > + }; > + > + reg_3p3v: regulator-3p3v { > + compatible = "regulator-fixed"; > + regulator-name = "3P3V"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-always-on; > + vin-supply = <®_12v>; > + }; > + > + reg_5p0v_hdd: regulator-5v-hdd { > + compatible = "regulator-fixed"; > + regulator-name = "5V_HDD"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + regulator-always-on; > + vin-supply = <®_12v>; > + }; > + > + reg_5p0v_usb: regulator-5v-usb { > + compatible = "regulator-fixed"; > + regulator-name = "USB-PWR"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + regulator-boot-on; > + regulator-always-on; > + enable-active-high; > + gpio = <&expander0 6 GPIO_ACTIVE_HIGH>; > + vin-supply = <®_12v>; > + }; > + > + system-leds { > + compatible = "gpio-leds"; > + status-led { > + label = "helios4:green:status"; > + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; > + linux,default-trigger = "heartbeat"; > + default-state = "on"; > + }; > + > + fault-led { > + label = "helios4:red:fault"; > + gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; > + default-state = "keep"; > + }; > + }; > + > + io-leds { > + compatible = "gpio-leds"; > + sata1-led { > + label = "helios4:green:ata1"; > + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; > + linux,default-trigger = "ata1"; > + default-state = "off"; > + }; > + sata2-led { > + label = "helios4:green:ata2"; > + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; > + linux,default-trigger = "ata2"; > + default-state = "off"; > + }; > + sata3-led { > + label = "helios4:green:ata3"; > + gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; > + linux,default-trigger = "ata3"; > + default-state = "off"; > + }; > + sata4-led { > + label = "helios4:green:ata4"; > + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; > + linux,default-trigger = "ata4"; > + default-state = "off"; > + }; > + usb-led { > + label = "helios4:green:usb"; > + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; > + linux,default-trigger = "usb-host"; > + default-state = "off"; > + }; > + }; > + > + fan1: j10-pwm { > + compatible = "pwm-fan"; > + pwms = <&gpio1 9 40000>; /* Target freq:25 kHz */ > + }; > + > + fan2: j17-pwm { > + compatible = "pwm-fan"; > + pwms = <&gpio1 23 40000>; /* Target freq:25 kHz */ > + }; > + > + usb2_phy: usb2-phy { > + compatible = "usb-nop-xceiv"; > + vbus-regulator = <®_5p0v_usb>; > + }; > + > + usb3_phy: usb3-phy { > + compatible = "usb-nop-xceiv"; > + //vbus-regulator = <®_5p0v_usb>; > + }; > + > + soc { > + internal-regs { > + i2c@11000 { > + clock-frequency = <400000>; > + pinctrl-0 = <&i2c0_pins>; > + pinctrl-names = "default"; > + status = "okay"; > + > + /* > + * PCA9655 GPIO expander, up to 1MHz clock. > + * 0-Board Revision bit 0 # > + * 1-Board Revision bit 1 # > + * 5-USB3 overcurrent > + * 6-USB3 power > + */ > + expander0: gpio-expander@20 { > + /* > + * This is how it should be: > + * compatible = "onnn,pca9655", > + * "nxp,pca9555"; > + * but you can't do this because of > + * the way I2C works. > + */ > + compatible = "nxp,pca9555"; > + gpio-controller; > + #gpio-cells = <2>; > + reg = <0x20>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pca0_pins>; > + interrupt-parent = <&gpio0>; > + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; > + interrupt-controller; > + #interrupt-cells = <2>; > + > + board_rev_bit_0 { > + gpio-hog; > + gpios = <0 GPIO_ACTIVE_LOW>; > + input; > + line-name = "board-rev-0"; > + }; > + board_rev_bit_1 { > + gpio-hog; > + gpios = <1 GPIO_ACTIVE_LOW>; > + input; > + line-name = "board-rev-1"; > + }; > + usb3_ilimit { > + gpio-hog; > + gpios = <5 GPIO_ACTIVE_HIGH>; > + input; > + line-name = "usb-overcurrent-status"; > + }; > + }; > + > + temp_sensor: temp@4c { > + compatible = "ti,lm75"; > + reg = <0x4c>; > + vcc-supply = <®_3p3v>; > + }; > + }; > + > + i2c@11100 { > + /* > + * External I2C Bus for user peripheral > + */ > + clock-frequency = <400000>; > + pinctrl-0 = <&helios_i2c1_pins>; > + pinctrl-names = "default"; > + status = "okay"; > + }; > + > + sata@a8000 { > + status = "okay"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + sata0: sata-port@0 { > + reg = <0>; > + }; > + > + sata1: sata-port@1 { > + reg = <1>; > + }; > + }; > + > + sata@e0000 { > + status = "okay"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + sata2: sata-port@0 { > + reg = <0>; > + }; > + > + sata3: sata-port@1 { > + reg = <1>; > + }; > + }; > + > + spi@10680 { > + pinctrl-0 = <&spi1_pins > + µsom_spi1_cs_pins>; > + pinctrl-names = "default"; > + status = "okay"; > + }; > + > + sdhci@d8000 { > + bus-width = <4>; > + cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; > + no-1-8-v; > + pinctrl-0 = <&helios_sdhci_pins > + &helios_sdhci_cd_pins>; > + pinctrl-names = "default"; > + status = "okay"; > + vmmc = <®_3p3v>; > + wp-inverted; > + }; > + > + usb@58000 { > + //vcc-supply = <®_5p0v_usb>; > + usb-phy = <&usb2_phy>; > + status = "okay"; > + }; > + > + usb3@f0000 { > + status = "okay"; > + }; > + > + usb3@f8000 { > + status = "okay"; > + }; > + > + pinctrl@18000 { > + pca0_pins: pca0-pins { > + marvell,pins = "mpp23"; > + marvell,function = "gpio"; > + }; > + microsom_phy0_int_pins: microsom-phy0-int-pins { > + marvell,pins = "mpp18"; > + marvell,function = "gpio"; > + }; > + helios_i2c1_pins: i2c1-pins { > + marvell,pins = "mpp26", "mpp27"; > + marvell,function = "i2c1"; > + }; > + helios_sdhci_cd_pins: helios-sdhci-cd-pins { > + marvell,pins = "mpp20"; > + marvell,function = "gpio"; > + }; > + helios_sdhci_pins: helios-sdhci-pins { > + marvell,pins = "mpp21", "mpp28", > + "mpp37", "mpp38", > + "mpp39", "mpp40"; > + marvell,function = "sd0"; > + }; > + helios_led_pins: helios-led-pins { > + marvell,pins = "mpp24", "mpp25", > + "mpp49", "mpp50", > + "mpp52", "mpp53", > + "mpp54"; > + marvell,function = "gpio"; > + }; > + helios_fan_pins: helios-fan-pins { > + marvell,pins = "mpp41", "mpp43", > + "mpp48", "mpp55"; > + marvell,function = "gpio"; > + }; > + microsom_spi1_cs_pins: spi1-cs-pins { > + marvell,pins = "mpp59"; > + marvell,function = "spi1"; > + }; > + }; > + }; > + }; > +}; > diff --git a/arch/arm/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/dts/armada-38x-solidrun-microsom.dtsi > new file mode 100644 > index 0000000000..7c1c7900ce > --- /dev/null > +++ b/arch/arm/dts/armada-38x-solidrun-microsom.dtsi > @@ -0,0 +1,100 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Device Tree file for SolidRun Armada 38x Microsom > + * > + * Copyright (C) 2015 Russell King > + * > + * This board is in development; the contents of this file work with > + * the A1 rev 2.0 of the board, which does not represent final > + * production board. Things will change, don't expect this file to > + * remain compatible info the future. > + */ > +#include <dt-bindings/input/input.h> > +#include <dt-bindings/gpio/gpio.h> > + > +/ { > + memory { > + device_type = "memory"; > + reg = <0x00000000 0x10000000>; /* 256 MB */ > + }; > + > + soc { > + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 > + MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 > + MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000 > + MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000 > + MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>; > + > + internal-regs { > + rtc@a3800 { > + /* > + * If the rtc doesn't work, run "date reset" > + * twice in u-boot. > + */ > + status = "okay"; > + }; > + }; > + }; > +}; > + > +ð0 { > + /* ethernet@70000 */ > + pinctrl-0 = <&ge0_rgmii_pins>; > + pinctrl-names = "default"; > + phy = <&phy_dedicated>; > + phy-mode = "rgmii-id"; > + status = "okay"; > +}; > + > +&mdio { > + /* > + * Add the phy clock here, so the phy can be accessed to read its > + * IDs prior to binding with the driver. > + */ > + pinctrl-0 = <&mdio_pins µsom_phy_clk_pins>; > + pinctrl-names = "default"; > + > + phy_dedicated: ethernet-phy@0 { > + /* > + * Annoyingly, the marvell phy driver configures the LED > + * register, rather than preserving reset-loaded setting. > + * We undo that rubbish here. > + */ > + marvell,reg-init = <3 16 0 0x101e>; > + reg = <0>; > + }; > +}; > + > +&pinctrl { > + microsom_phy_clk_pins: microsom-phy-clk-pins { > + marvell,pins = "mpp45"; > + marvell,function = "ref"; > + }; > + /* Optional eMMC */ > + microsom_sdhci_pins: microsom-sdhci-pins { > + marvell,pins = "mpp21", "mpp28", "mpp37", > + "mpp38", "mpp39", "mpp40"; > + marvell,function = "sd0"; > + }; > +}; > + > +&spi1 { > + /* The microsom has an optional W25Q32 on board, connected to CS0 */ > + pinctrl-0 = <&spi1_pins>; > + > + w25q32: spi-flash@0 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "w25q32", "jedec,spi-nor"; > + reg = <0>; /* Chip select 0 */ > + spi-max-frequency = <3000000>; > + status = "disabled"; > + }; > +}; > + > +&uart0 { > + pinctrl-0 = <&uart0_pins>; > + pinctrl-names = "default"; > + status = "okay"; > + u-boot,dm-pre-reloc; > +}; > diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig > index f431cff950..0b47642d0c 100644 > --- a/arch/arm/mach-mvebu/Kconfig > +++ b/arch/arm/mach-mvebu/Kconfig > @@ -75,6 +75,10 @@ config TARGET_CLEARFOG > bool "Support ClearFog" > select 88F6820 > > +config TARGET_HELIOS4 > + bool "Support Helios4" > + select 88F6820 > + > config TARGET_MVEBU_ARMADA_37XX > bool "Support Armada 37xx platforms" > select ARMADA_3700 > @@ -132,6 +136,7 @@ endchoice > > config SYS_BOARD > default "clearfog" if TARGET_CLEARFOG > + default "helios4" if TARGET_HELIOS4 > default "mvebu_armada-37xx" if TARGET_MVEBU_ARMADA_37XX > default "db-88f6720" if TARGET_DB_88F6720 > default "db-88f6820-gp" if TARGET_DB_88F6820_GP > @@ -146,6 +151,7 @@ config SYS_BOARD > > config SYS_CONFIG_NAME > default "clearfog" if TARGET_CLEARFOG > + default "helios4" if TARGET_HELIOS4 > default "mvebu_armada-37xx" if TARGET_MVEBU_ARMADA_37XX > default "db-88f6720" if TARGET_DB_88F6720 > default "db-88f6820-gp" if TARGET_DB_88F6820_GP > @@ -166,6 +172,7 @@ config SYS_VENDOR > default "Marvell" if TARGET_DB_88F6820_AMC > default "Marvell" if TARGET_MVEBU_ARMADA_8K > default "solidrun" if TARGET_CLEARFOG > + default "solidrun" if TARGET_HELIOS4 > default "Synology" if TARGET_DS414 > default "CZ.NIC" if TARGET_TURRIS_OMNIA > default "CZ.NIC" if TARGET_TURRIS_MOX > diff --git a/board/solidrun/helios4/MAINTAINERS b/board/solidrun/helios4/MAINTAINERS > new file mode 100644 > index 0000000000..02e31a8768 > --- /dev/null > +++ b/board/solidrun/helios4/MAINTAINERS > @@ -0,0 +1,6 @@ > +HELIOS4 BOARD > +M: Stefan Roese <sr@denx.de> You've updated the files but should this be M: Dennis Gilmore? > +S: Maintained > +F: board/soldrun/helios4/ > +F: include/configs/helios4.h > +F: configs/helios4_defconfig > diff --git a/board/solidrun/helios4/Makefile b/board/solidrun/helios4/Makefile > new file mode 100644 > index 0000000000..84be38c572 > --- /dev/null > +++ b/board/solidrun/helios4/Makefile > @@ -0,0 +1,5 @@ > +# SPDX-License-Identifier: GPL-2.0+ > +# > +# Copyright (C) 2015 Stefan Roese <sr@denx.de> You can probably assign this copyright to yourself or your employer. > + > +obj-y := helios4.o > diff --git a/board/solidrun/helios4/README b/board/solidrun/helios4/README > new file mode 100644 > index 0000000000..cf90bf9d83 > --- /dev/null > +++ b/board/solidrun/helios4/README > @@ -0,0 +1,46 @@ > +Update from original Marvell U-Boot to mainline U-Boot: > +------------------------------------------------------- > + > +Generate the U-Boot image with these commands: > + > +$ make helios4_defconfig > +$ make > + > +The resulting image including the SPL binary with the > +full DDR setup is "u-boot-spl.kwb". > + > +Now all you need to do is copy this image on a SD card. > +For example with this command: > + > +$ sudo dd if=u-boot-spl.kwb of=/dev/sdX bs=512 seek=1 > + > +Please use the correct device node for your setup instead > +of "/dev/sdX" here! > + > +Boot selection: > +--------------- > + > +Before powering up the board, boot selection should be done via the SW1 dip > +switch (0: OFF, 1: ON): > + > + - SPI: 00010 > + - SD/eMMC: 00111 > + - SATA1: 11100 > + - UART: 11110 > + > +Boot from UART: > +--------------- > + > +Connect the on-board micro-USB (CF Pro: CON11, CF Base: CON5) > +to your host. > + > +Set the SW1 DIP switches to UART boot (see above). > + > +Run the following command to initiate U-Boot download: > + > + ./tools/kwboot -p u-boot-spl.kwb /dev/ttyUSBX Sorry, I meant you need both -p and -b. > + > +Use the correct UART device node for /dev/ttyUSBX. > + > +When download finishes start your favorite terminal emulator > +on /dev/ttyUSBX. > diff --git a/board/solidrun/helios4/helios4.c b/board/solidrun/helios4/helios4.c > new file mode 100644 > index 0000000000..372f40285a > --- /dev/null > +++ b/board/solidrun/helios4/helios4.c > @@ -0,0 +1,172 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2015 Stefan Roese <sr@denx.de> Not sure about this one. I guess copyright Dennis based on clearfog.c? > + */ > + > +#include <common.h> > +#include <i2c.h> > +#include <miiphy.h> > +#include <netdev.h> > +#include <asm/io.h> > +#include <asm/arch/cpu.h> > +#include <asm/arch/soc.h> > + > +#include "../drivers/ddr/marvell/a38x/ddr3_init.h" > +#include <../serdes/a38x/high_speed_env_spec.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +#define ETH_PHY_CTRL_REG 0 > +#define ETH_PHY_CTRL_POWER_DOWN_BIT 11 > +#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) > + > +/* > + * Those values and defines are taken from the Marvell U-Boot version > + * "u-boot-2013.01-15t1-helios4" as well as the upstream config for clearfog > + */ > +#define BOARD_GPP_OUT_ENA_LOW 0xffffffff > +#define BOARD_GPP_OUT_ENA_MID 0xffffffff > + > +#define BOARD_GPP_OUT_VAL_LOW 0x0 > +#define BOARD_GPP_OUT_VAL_MID 0x0 > +#define BOARD_GPP_POL_LOW 0x0 > +#define BOARD_GPP_POL_MID 0x0 > + > +/* IO expander on Marvell GP board includes e.g. fan enabling */ > +struct marvell_io_exp { > + u8 addr; > + u8 val; > +}; > + > +static struct marvell_io_exp io_exp[] = { > + {6, 0xf9}, > + {2, 0x46}, /* Assert reset signals and enable USB3 current limiter */ > + {6, 0xb9} > +}; > + > +static struct serdes_map board_serdes_map[] = { > + {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0}, > + {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, > + {SATA1, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0}, > + {SATA3, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0}, > + {SATA2, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0}, > + {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, > +}; > + > +int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) > +{ > + *serdes_map_array = board_serdes_map; > + *count = ARRAY_SIZE(board_serdes_map); > + return 0; > +} > + > +/* > + * Define the DDR layout / topology here in the board file. This will > + * be used by the DDR3 init code in the SPL U-Boot version to configure > + * the DDR3 controller. > + */ > +static struct mv_ddr_topology_map board_topology_map = { > + DEBUG_LEVEL_ERROR, > + 0x1, /* active interfaces */ > + /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ > + { { { {0x1, 0, 0, 0}, > + {0x1, 0, 0, 0}, > + {0x1, 0, 0, 0}, > + {0x1, 0, 0, 0}, > + {0x1, 0, 0, 0} }, > + SPEED_BIN_DDR_1600K, /* speed_bin */ > + MV_DDR_DEV_WIDTH_16BIT, /* memory_width */ > + MV_DDR_DIE_CAP_8GBIT, /* mem_size */ > + DDR_FREQ_800, /* frequency */ > + 0, 0, /* cas_wl cas_l */ > + MV_DDR_TEMP_LOW, /* temperature */ > + MV_DDR_TIM_DEFAULT} }, /* timing */ > + BUS_MASK_32BIT_ECC, /* Busses mask */ > + MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ > + { {0} }, /* raw spd data */ > + {0} /* timing parameters */ > +}; > + > +struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) > +{ > + /* Return the board topology as defined in the board code */ > + return &board_topology_map; > +} > + > +int board_early_init_f(void) > +{ > + /* Configure MPP */ > + writel(0x11111111, MVEBU_MPP_BASE + 0x00); > + writel(0x11111111, MVEBU_MPP_BASE + 0x04); > + writel(0x10400011, MVEBU_MPP_BASE + 0x08); > + writel(0x22043333, MVEBU_MPP_BASE + 0x0c); > + writel(0x44400002, MVEBU_MPP_BASE + 0x10); > + writel(0x41144004, MVEBU_MPP_BASE + 0x14); > + writel(0x40333333, MVEBU_MPP_BASE + 0x18); > + writel(0x00004444, MVEBU_MPP_BASE + 0x1c); > + > + /* Set GPP Out value */ > + writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); > + writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); > + > + /* Set GPP Polarity */ > + writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); > + writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); > + > + /* Set GPP Out Enable */ > + writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); > + writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); Technically these GPP values are the hardware defualts so I'm not sure this is having any effect. It might be undoing some settings from the previous boot but I think these will be restored by the SYSRESET. > + > + return 0; > +} > + > +int board_init(void) > +{ > + int i; > + > + /* Address of boot parameters */ > + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; > + > + /* Toggle GPIO41 to reset onboard switch and phy */ > + clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9)); > + clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9)); > + /* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */ > + clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19)); > + clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19)); > + mdelay(1); > + setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9)); > + setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19)); > + mdelay(10); When you get round to it (for a follow up patch). It'll be something like this // dts some-node { some-gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>, <&gpio1 9 GPIO_ACTIVE_HIGH>; }; // C code struct gpio_desc gpios[2]; int node; node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "some-node"); gpio_request_list_by_name_nodev(offset_to_ofnode(node), "some-gpio", 2, &gpio); dm_gpio_set_value(&gpio[0], 0); dm_gpio_set_value(&gpio[1], 0); mdelay(); dm_gpio_set_value(&gpio[0], 1); dm_gpio_set_value(&gpio[1], 1); > + > + /* Init I2C IO expanders */ > + for (i = 0; i < ARRAY_SIZE(io_exp); i++) { > + struct udevice *dev; > + int ret; > + ret = i2c_get_chip_for_busnum(0, io_exp[i].addr, 1, &dev); > + if (ret) { > + printf("Cannot find I2C: %d\n", ret); > + return 0; > + } > + > + ret = dm_i2c_write(dev, io_exp[i].val, &io_exp[i].val, 1); > + if (ret) { > + printf("Failed to set IO expander via I2C\n"); > + return -EIO; > + } > + } > + > + return 0; > +} > + > +int checkboard(void) > +{ > + puts("Board: Helios4\n"); > + > + return 0; > +} > + > +int board_eth_init(bd_t *bis) > +{ > + cpu_eth_init(bis); /* Built in controller(s) come first */ > + return pci_eth_init(bis); > +} > diff --git a/board/solidrun/helios4/kwbimage.cfg b/board/solidrun/helios4/kwbimage.cfg > new file mode 100644 > index 0000000000..035063bc90 > --- /dev/null > +++ b/board/solidrun/helios4/kwbimage.cfg > @@ -0,0 +1,13 @@ > +# SPDX-License-Identifier: GPL-2.0+ > +# > +# Copyright (C) 2015 Stefan Roese <sr@denx.de> > +# > + > +# Armada 38x use version 1 image format > +VERSION 1 > + > +# Boot Media configurations > +BOOT_FROM sdio > + > +# Binary Header (bin_hdr) with DDR3 training code > +BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068 > diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig > new file mode 100644 > index 0000000000..b72428555d > --- /dev/null > +++ b/configs/helios4_defconfig > @@ -0,0 +1,58 @@ > +CONFIG_ARM=y > +CONFIG_ARCH_MVEBU=y > +CONFIG_SYS_TEXT_BASE=0x00800000 > +CONFIG_SPL_LIBCOMMON_SUPPORT=y > +CONFIG_SPL_LIBGENERIC_SUPPORT=y > +CONFIG_SYS_MALLOC_F_LEN=0x2000 > +CONFIG_TARGET_HELIOS4=y > +CONFIG_SPL_MMC_SUPPORT=y > +CONFIG_SPL_SERIAL_SUPPORT=y > +CONFIG_SPL_LIBDISK_SUPPORT=y > +CONFIG_SPL=y > +CONFIG_DEFAULT_DEVICE_TREE="armada-388-helios4" > +CONFIG_DEBUG_UART=y > +CONFIG_DISTRO_DEFAULTS=y > +CONFIG_BOOTDELAY=3 > +CONFIG_SYS_CONSOLE_INFO_QUIET=y > +# CONFIG_DISPLAY_BOARDINFO is not set > +CONFIG_DISPLAY_BOARDINFO_LATE=y > +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x141 > +CONFIG_SPL_I2C_SUPPORT=y > +# CONFIG_CMD_FLASH is not set > +CONFIG_CMD_I2C=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_PCI=y > +CONFIG_CMD_SF=y > +CONFIG_CMD_SPI=y > +CONFIG_CMD_USB=y > +# CONFIG_CMD_SETEXPR is not set > +CONFIG_CMD_TFTPPUT=y > +CONFIG_CMD_CACHE=y > +CONFIG_CMD_TIME=y > +# CONFIG_SPL_PARTITION_UUIDS is not set > +CONFIG_ENV_IS_IN_MMC=y > +CONFIG_NET_RANDOM_ETHADDR=y > +CONFIG_SPL_OF_TRANSLATE=y > +CONFIG_MMC_SDHCI=y > +CONFIG_MMC_SDHCI_SDMA=y > +CONFIG_MMC_SDHCI_MV=y > +CONFIG_AHCI=y > +CONFIG_SCSI_AHCI=y > +CONFIG_SCSI=y > +CONFIG_SPI_FLASH=y > +CONFIG_SPI_FLASH_BAR=y > +CONFIG_SPI_FLASH_WINBOND=y > +CONFIG_SPI_FLASH_MTD=y > +CONFIG_PHY_GIGE=y > +CONFIG_MVNETA=y > +CONFIG_PCI=y > +CONFIG_DEBUG_UART_BASE=0xd0012000 > +CONFIG_DEBUG_UART_CLOCK=250000000 > +CONFIG_DEBUG_UART_SHIFT=2 > +CONFIG_SYS_NS16550=y > +CONFIG_KIRKWOOD_SPI=y > +CONFIG_USB=y > +CONFIG_DM_USB=y > +CONFIG_DM_I2C=y > +CONFIG_USB_XHCI_HCD=y > +CONFIG_USB_STORAGE=y > diff --git a/include/configs/helios4.h b/include/configs/helios4.h > new file mode 100644 > index 0000000000..5a4b7055fa > --- /dev/null > +++ b/include/configs/helios4.h > @@ -0,0 +1,178 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright (C) 2015 Stefan Roese <sr@denx.de> > + */ > + > +#ifndef _CONFIG_HELIOS4_H > +#define _CONFIG_HELIOS4_H > + > +/* > + * High Level Configuration Options (easy to change) > + */ > + > +/* > + * TEXT_BASE needs to be below 16MiB, since this area is scrubbed > + * for DDR ECC byte filling in the SPL before loading the main > + * U-Boot into it. > + */ > +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ > + > +/* > + * Commands configuration > + */ > + > +/* SPI NOR flash default params, used by sf commands */ > +#define CONFIG_SF_DEFAULT_BUS 1 > + > +/* > + * SDIO/MMC Card Configuration > + */ > +#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE > + > +/* USB/EHCI configuration */ > +#define CONFIG_EHCI_IS_TDI > + > +#define CONFIG_ENV_MIN_ENTRIES 128 > + > +/* > + * SATA/SCSI/AHCI configuration > + */ > +#define CONFIG_SCSI_AHCI_PLAT > +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 > +#define CONFIG_SYS_SCSI_MAX_LUN 2 > +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ > + CONFIG_SYS_SCSI_MAX_LUN) > + > +/* Environment in MMC */ > +#define CONFIG_SYS_MMC_ENV_DEV 0 > +#define CONFIG_ENV_SECT_SIZE 0x200 > +#define CONFIG_ENV_SIZE 0x10000 > +/* > + * For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC > + * boot image starts @ LBA-0. > + * As result in MMC/eMMC case it will be a 1 sector gap between u-boot > + * image and environment > + */ > +#define CONFIG_ENV_OFFSET 0xf0000 > +#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET > + > +#define CONFIG_PHY_MARVELL /* there is a marvell phy */ > +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ > + > +/* PCIe support */ > +#ifndef CONFIG_SPL_BUILD > +#define CONFIG_PCI_MVEBU > +#define CONFIG_PCI_SCAN_SHOW > +#endif > + > +/* Keep device tree and initrd in lower memory so the kernel can access them */ > +#define RELOCATION_LIMITS_ENV_SETTINGS \ > + "fdt_high=0x10000000\0" \ > + "initrd_high=0x10000000\0" > + > +/* SPL */ > +/* > + * Select the boot device here > + * > + * Currently supported are: > + * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash > + * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) > + */ > +#define SPL_BOOT_SPI_NOR_FLASH 1 > +#define SPL_BOOT_SDIO_MMC_CARD 2 > +#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SDIO_MMC_CARD > + > +/* Defines for SPL */ > +#define CONFIG_SPL_SIZE (140 << 10) > +#define CONFIG_SPL_TEXT_BASE 0x40000030 > +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) > + > +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) > +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) > + > +#ifdef CONFIG_SPL_BUILD > +#define CONFIG_SYS_MALLOC_SIMPLE > +#endif > + > +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) > +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) > + > +#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH > +/* SPL related SPI defines */ > +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 > +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS > +#endif > + > +#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD > +/* SPL related MMC defines */ > +#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) > +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS > +#ifdef CONFIG_SPL_BUILD > +#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ > +#endif > + > +/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ > +#define CONFIG_SPD_EEPROM 0x4e > +#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ The Armada-38x code doesn't use either of these defines (AXP does and I think the Marvell bin_hdr might). > + > +#endif > + > +/* > + * mv-common.h should be defined after CMD configs since it used them > + * to enable certain macros > + */ > +#include "mv-common.h" > + > +/* Include the common distro boot environment */ > +#ifndef CONFIG_SPL_BUILD > + > +#ifdef CONFIG_MMC > +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) > +#else > +#define BOOT_TARGET_DEVICES_MMC(func) > +#endif > + > +#ifdef CONFIG_USB_STORAGE > +#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) > +#else > +#define BOOT_TARGET_DEVICES_USB(func) > +#endif > + > +#ifdef CONFIG_SATA > +#define BOOT_TARGET_DEVICES_SATA(func) func(SATA, sata, 0) > +#else > +#define BOOT_TARGET_DEVICES_SATA(func) > +#endif > + > +#define BOOT_TARGET_DEVICES(func) \ > + BOOT_TARGET_DEVICES_MMC(func) \ > + BOOT_TARGET_DEVICES_USB(func) \ > + BOOT_TARGET_DEVICES_SATA(func) \ > + func(PXE, pxe, na) \ > + func(DHCP, dhcp, na) > + > +#define KERNEL_ADDR_R __stringify(0x800000) > +#define FDT_ADDR_R __stringify(0x100000) > +#define RAMDISK_ADDR_R __stringify(0x1800000) > +#define SCRIPT_ADDR_R __stringify(0x200000) > +#define PXEFILE_ADDR_R __stringify(0x300000) > + > +#define LOAD_ADDRESS_ENV_SETTINGS \ > + "kernel_addr_r=" KERNEL_ADDR_R "\0" \ > + "fdt_addr_r=" FDT_ADDR_R "\0" \ > + "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \ > + "scriptaddr=" SCRIPT_ADDR_R "\0" \ > + "pxefile_addr_r=" PXEFILE_ADDR_R "\0" > + > +#include <config_distro_bootcmd.h> > + > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + RELOCATION_LIMITS_ENV_SETTINGS \ > + LOAD_ADDRESS_ENV_SETTINGS \ > + "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ > + "console=ttyS0,115200\0" \ > + BOOTENV > + > +#endif /* CONFIG_SPL_BUILD */ > + > +#endif /* _CONFIG_HELIOS4_H */ > -- > 2.17.1 >
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a0349a8975..a18f4bbf7b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -91,6 +91,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-375-db.dtb \ armada-388-clearfog.dtb \ armada-388-gp.dtb \ + armada-388-helios4.dtb \ armada-385-amc.dtb \ armada-7040-db.dtb \ armada-7040-db-nand.dtb \ diff --git a/arch/arm/dts/armada-388-helios4.dts b/arch/arm/dts/armada-388-helios4.dts new file mode 100644 index 0000000000..3223e4d71f --- /dev/null +++ b/arch/arm/dts/armada-388-helios4.dts @@ -0,0 +1,308 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +#include "armada-388.dtsi" +#include "armada-38x-solidrun-microsom.dtsi" + +/ { + model = "Helios4"; + compatible = "solidrun,helios4", "marvell,armada388", + "marvell,armada385", "marvell,armada380"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000>; /* 2 GB */ + }; + + aliases { + /* So that mvebu u-boot can update the MAC addresses */ + ethernet1 = ð0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_12v: regulator-12v { + compatible = "regulator-fixed"; + regulator-name = "power_brick_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_12v>; + }; + + reg_5p0v_hdd: regulator-5v-hdd { + compatible = "regulator-fixed"; + regulator-name = "5V_HDD"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <®_12v>; + }; + + reg_5p0v_usb: regulator-5v-usb { + compatible = "regulator-fixed"; + regulator-name = "USB-PWR"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&expander0 6 GPIO_ACTIVE_HIGH>; + vin-supply = <®_12v>; + }; + + system-leds { + compatible = "gpio-leds"; + status-led { + label = "helios4:green:status"; + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + fault-led { + label = "helios4:red:fault"; + gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + }; + + io-leds { + compatible = "gpio-leds"; + sata1-led { + label = "helios4:green:ata1"; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + linux,default-trigger = "ata1"; + default-state = "off"; + }; + sata2-led { + label = "helios4:green:ata2"; + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + linux,default-trigger = "ata2"; + default-state = "off"; + }; + sata3-led { + label = "helios4:green:ata3"; + gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + linux,default-trigger = "ata3"; + default-state = "off"; + }; + sata4-led { + label = "helios4:green:ata4"; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; + linux,default-trigger = "ata4"; + default-state = "off"; + }; + usb-led { + label = "helios4:green:usb"; + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; + linux,default-trigger = "usb-host"; + default-state = "off"; + }; + }; + + fan1: j10-pwm { + compatible = "pwm-fan"; + pwms = <&gpio1 9 40000>; /* Target freq:25 kHz */ + }; + + fan2: j17-pwm { + compatible = "pwm-fan"; + pwms = <&gpio1 23 40000>; /* Target freq:25 kHz */ + }; + + usb2_phy: usb2-phy { + compatible = "usb-nop-xceiv"; + vbus-regulator = <®_5p0v_usb>; + }; + + usb3_phy: usb3-phy { + compatible = "usb-nop-xceiv"; + //vbus-regulator = <®_5p0v_usb>; + }; + + soc { + internal-regs { + i2c@11000 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* + * PCA9655 GPIO expander, up to 1MHz clock. + * 0-Board Revision bit 0 # + * 1-Board Revision bit 1 # + * 5-USB3 overcurrent + * 6-USB3 power + */ + expander0: gpio-expander@20 { + /* + * This is how it should be: + * compatible = "onnn,pca9655", + * "nxp,pca9555"; + * but you can't do this because of + * the way I2C works. + */ + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pca0_pins>; + interrupt-parent = <&gpio0>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + board_rev_bit_0 { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + input; + line-name = "board-rev-0"; + }; + board_rev_bit_1 { + gpio-hog; + gpios = <1 GPIO_ACTIVE_LOW>; + input; + line-name = "board-rev-1"; + }; + usb3_ilimit { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + input; + line-name = "usb-overcurrent-status"; + }; + }; + + temp_sensor: temp@4c { + compatible = "ti,lm75"; + reg = <0x4c>; + vcc-supply = <®_3p3v>; + }; + }; + + i2c@11100 { + /* + * External I2C Bus for user peripheral + */ + clock-frequency = <400000>; + pinctrl-0 = <&helios_i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + sata@a8000 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + sata0: sata-port@0 { + reg = <0>; + }; + + sata1: sata-port@1 { + reg = <1>; + }; + }; + + sata@e0000 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + sata2: sata-port@0 { + reg = <0>; + }; + + sata3: sata-port@1 { + reg = <1>; + }; + }; + + spi@10680 { + pinctrl-0 = <&spi1_pins + µsom_spi1_cs_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + sdhci@d8000 { + bus-width = <4>; + cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + no-1-8-v; + pinctrl-0 = <&helios_sdhci_pins + &helios_sdhci_cd_pins>; + pinctrl-names = "default"; + status = "okay"; + vmmc = <®_3p3v>; + wp-inverted; + }; + + usb@58000 { + //vcc-supply = <®_5p0v_usb>; + usb-phy = <&usb2_phy>; + status = "okay"; + }; + + usb3@f0000 { + status = "okay"; + }; + + usb3@f8000 { + status = "okay"; + }; + + pinctrl@18000 { + pca0_pins: pca0-pins { + marvell,pins = "mpp23"; + marvell,function = "gpio"; + }; + microsom_phy0_int_pins: microsom-phy0-int-pins { + marvell,pins = "mpp18"; + marvell,function = "gpio"; + }; + helios_i2c1_pins: i2c1-pins { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "i2c1"; + }; + helios_sdhci_cd_pins: helios-sdhci-cd-pins { + marvell,pins = "mpp20"; + marvell,function = "gpio"; + }; + helios_sdhci_pins: helios-sdhci-pins { + marvell,pins = "mpp21", "mpp28", + "mpp37", "mpp38", + "mpp39", "mpp40"; + marvell,function = "sd0"; + }; + helios_led_pins: helios-led-pins { + marvell,pins = "mpp24", "mpp25", + "mpp49", "mpp50", + "mpp52", "mpp53", + "mpp54"; + marvell,function = "gpio"; + }; + helios_fan_pins: helios-fan-pins { + marvell,pins = "mpp41", "mpp43", + "mpp48", "mpp55"; + marvell,function = "gpio"; + }; + microsom_spi1_cs_pins: spi1-cs-pins { + marvell,pins = "mpp59"; + marvell,function = "spi1"; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/dts/armada-38x-solidrun-microsom.dtsi new file mode 100644 index 0000000000..7c1c7900ce --- /dev/null +++ b/arch/arm/dts/armada-38x-solidrun-microsom.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for SolidRun Armada 38x Microsom + * + * Copyright (C) 2015 Russell King + * + * This board is in development; the contents of this file work with + * the A1 rev 2.0 of the board, which does not represent final + * production board. Things will change, don't expect this file to + * remain compatible info the future. + */ +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; /* 256 MB */ + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 + MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000 + MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000 + MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>; + + internal-regs { + rtc@a3800 { + /* + * If the rtc doesn't work, run "date reset" + * twice in u-boot. + */ + status = "okay"; + }; + }; + }; +}; + +ð0 { + /* ethernet@70000 */ + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + phy = <&phy_dedicated>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&mdio { + /* + * Add the phy clock here, so the phy can be accessed to read its + * IDs prior to binding with the driver. + */ + pinctrl-0 = <&mdio_pins µsom_phy_clk_pins>; + pinctrl-names = "default"; + + phy_dedicated: ethernet-phy@0 { + /* + * Annoyingly, the marvell phy driver configures the LED + * register, rather than preserving reset-loaded setting. + * We undo that rubbish here. + */ + marvell,reg-init = <3 16 0 0x101e>; + reg = <0>; + }; +}; + +&pinctrl { + microsom_phy_clk_pins: microsom-phy-clk-pins { + marvell,pins = "mpp45"; + marvell,function = "ref"; + }; + /* Optional eMMC */ + microsom_sdhci_pins: microsom-sdhci-pins { + marvell,pins = "mpp21", "mpp28", "mpp37", + "mpp38", "mpp39", "mpp40"; + marvell,function = "sd0"; + }; +}; + +&spi1 { + /* The microsom has an optional W25Q32 on board, connected to CS0 */ + pinctrl-0 = <&spi1_pins>; + + w25q32: spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "w25q32", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <3000000>; + status = "disabled"; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index f431cff950..0b47642d0c 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -75,6 +75,10 @@ config TARGET_CLEARFOG bool "Support ClearFog" select 88F6820 +config TARGET_HELIOS4 + bool "Support Helios4" + select 88F6820 + config TARGET_MVEBU_ARMADA_37XX bool "Support Armada 37xx platforms" select ARMADA_3700 @@ -132,6 +136,7 @@ endchoice config SYS_BOARD default "clearfog" if TARGET_CLEARFOG + default "helios4" if TARGET_HELIOS4 default "mvebu_armada-37xx" if TARGET_MVEBU_ARMADA_37XX default "db-88f6720" if TARGET_DB_88F6720 default "db-88f6820-gp" if TARGET_DB_88F6820_GP @@ -146,6 +151,7 @@ config SYS_BOARD config SYS_CONFIG_NAME default "clearfog" if TARGET_CLEARFOG + default "helios4" if TARGET_HELIOS4 default "mvebu_armada-37xx" if TARGET_MVEBU_ARMADA_37XX default "db-88f6720" if TARGET_DB_88F6720 default "db-88f6820-gp" if TARGET_DB_88F6820_GP @@ -166,6 +172,7 @@ config SYS_VENDOR default "Marvell" if TARGET_DB_88F6820_AMC default "Marvell" if TARGET_MVEBU_ARMADA_8K default "solidrun" if TARGET_CLEARFOG + default "solidrun" if TARGET_HELIOS4 default "Synology" if TARGET_DS414 default "CZ.NIC" if TARGET_TURRIS_OMNIA default "CZ.NIC" if TARGET_TURRIS_MOX diff --git a/board/solidrun/helios4/MAINTAINERS b/board/solidrun/helios4/MAINTAINERS new file mode 100644 index 0000000000..02e31a8768 --- /dev/null +++ b/board/solidrun/helios4/MAINTAINERS @@ -0,0 +1,6 @@ +HELIOS4 BOARD +M: Stefan Roese <sr@denx.de> +S: Maintained +F: board/soldrun/helios4/ +F: include/configs/helios4.h +F: configs/helios4_defconfig diff --git a/board/solidrun/helios4/Makefile b/board/solidrun/helios4/Makefile new file mode 100644 index 0000000000..84be38c572 --- /dev/null +++ b/board/solidrun/helios4/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2015 Stefan Roese <sr@denx.de> + +obj-y := helios4.o diff --git a/board/solidrun/helios4/README b/board/solidrun/helios4/README new file mode 100644 index 0000000000..cf90bf9d83 --- /dev/null +++ b/board/solidrun/helios4/README @@ -0,0 +1,46 @@ +Update from original Marvell U-Boot to mainline U-Boot: +------------------------------------------------------- + +Generate the U-Boot image with these commands: + +$ make helios4_defconfig +$ make + +The resulting image including the SPL binary with the +full DDR setup is "u-boot-spl.kwb". + +Now all you need to do is copy this image on a SD card. +For example with this command: + +$ sudo dd if=u-boot-spl.kwb of=/dev/sdX bs=512 seek=1 + +Please use the correct device node for your setup instead +of "/dev/sdX" here! + +Boot selection: +--------------- + +Before powering up the board, boot selection should be done via the SW1 dip +switch (0: OFF, 1: ON): + + - SPI: 00010 + - SD/eMMC: 00111 + - SATA1: 11100 + - UART: 11110 + +Boot from UART: +--------------- + +Connect the on-board micro-USB (CF Pro: CON11, CF Base: CON5) +to your host. + +Set the SW1 DIP switches to UART boot (see above). + +Run the following command to initiate U-Boot download: + + ./tools/kwboot -p u-boot-spl.kwb /dev/ttyUSBX + +Use the correct UART device node for /dev/ttyUSBX. + +When download finishes start your favorite terminal emulator +on /dev/ttyUSBX. diff --git a/board/solidrun/helios4/helios4.c b/board/solidrun/helios4/helios4.c new file mode 100644 index 0000000000..372f40285a --- /dev/null +++ b/board/solidrun/helios4/helios4.c @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Stefan Roese <sr@denx.de> + */ + +#include <common.h> +#include <i2c.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> + +#include "../drivers/ddr/marvell/a38x/ddr3_init.h" +#include <../serdes/a38x/high_speed_env_spec.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define ETH_PHY_CTRL_REG 0 +#define ETH_PHY_CTRL_POWER_DOWN_BIT 11 +#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) + +/* + * Those values and defines are taken from the Marvell U-Boot version + * "u-boot-2013.01-15t1-helios4" as well as the upstream config for clearfog + */ +#define BOARD_GPP_OUT_ENA_LOW 0xffffffff +#define BOARD_GPP_OUT_ENA_MID 0xffffffff + +#define BOARD_GPP_OUT_VAL_LOW 0x0 +#define BOARD_GPP_OUT_VAL_MID 0x0 +#define BOARD_GPP_POL_LOW 0x0 +#define BOARD_GPP_POL_MID 0x0 + +/* IO expander on Marvell GP board includes e.g. fan enabling */ +struct marvell_io_exp { + u8 addr; + u8 val; +}; + +static struct marvell_io_exp io_exp[] = { + {6, 0xf9}, + {2, 0x46}, /* Assert reset signals and enable USB3 current limiter */ + {6, 0xb9} +}; + +static struct serdes_map board_serdes_map[] = { + {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {SATA1, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {SATA3, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {SATA2, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, +}; + +int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) +{ + *serdes_map_array = board_serdes_map; + *count = ARRAY_SIZE(board_serdes_map); + return 0; +} + +/* + * Define the DDR layout / topology here in the board file. This will + * be used by the DDR3 init code in the SPL U-Boot version to configure + * the DDR3 controller. + */ +static struct mv_ddr_topology_map board_topology_map = { + DEBUG_LEVEL_ERROR, + 0x1, /* active interfaces */ + /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ + { { { {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0} }, + SPEED_BIN_DDR_1600K, /* speed_bin */ + MV_DDR_DEV_WIDTH_16BIT, /* memory_width */ + MV_DDR_DIE_CAP_8GBIT, /* mem_size */ + DDR_FREQ_800, /* frequency */ + 0, 0, /* cas_wl cas_l */ + MV_DDR_TEMP_LOW, /* temperature */ + MV_DDR_TIM_DEFAULT} }, /* timing */ + BUS_MASK_32BIT_ECC, /* Busses mask */ + MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ + { {0} }, /* raw spd data */ + {0} /* timing parameters */ +}; + +struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) +{ + /* Return the board topology as defined in the board code */ + return &board_topology_map; +} + +int board_early_init_f(void) +{ + /* Configure MPP */ + writel(0x11111111, MVEBU_MPP_BASE + 0x00); + writel(0x11111111, MVEBU_MPP_BASE + 0x04); + writel(0x10400011, MVEBU_MPP_BASE + 0x08); + writel(0x22043333, MVEBU_MPP_BASE + 0x0c); + writel(0x44400002, MVEBU_MPP_BASE + 0x10); + writel(0x41144004, MVEBU_MPP_BASE + 0x14); + writel(0x40333333, MVEBU_MPP_BASE + 0x18); + writel(0x00004444, MVEBU_MPP_BASE + 0x1c); + + /* Set GPP Out value */ + writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); + writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); + + /* Set GPP Polarity */ + writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); + writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); + + /* Set GPP Out Enable */ + writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); + writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); + + return 0; +} + +int board_init(void) +{ + int i; + + /* Address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + /* Toggle GPIO41 to reset onboard switch and phy */ + clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9)); + clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9)); + /* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */ + clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19)); + clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19)); + mdelay(1); + setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9)); + setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19)); + mdelay(10); + + /* Init I2C IO expanders */ + for (i = 0; i < ARRAY_SIZE(io_exp); i++) { + struct udevice *dev; + int ret; + ret = i2c_get_chip_for_busnum(0, io_exp[i].addr, 1, &dev); + if (ret) { + printf("Cannot find I2C: %d\n", ret); + return 0; + } + + ret = dm_i2c_write(dev, io_exp[i].val, &io_exp[i].val, 1); + if (ret) { + printf("Failed to set IO expander via I2C\n"); + return -EIO; + } + } + + return 0; +} + +int checkboard(void) +{ + puts("Board: Helios4\n"); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Built in controller(s) come first */ + return pci_eth_init(bis); +} diff --git a/board/solidrun/helios4/kwbimage.cfg b/board/solidrun/helios4/kwbimage.cfg new file mode 100644 index 0000000000..035063bc90 --- /dev/null +++ b/board/solidrun/helios4/kwbimage.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2015 Stefan Roese <sr@denx.de> +# + +# Armada 38x use version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM sdio + +# Binary Header (bin_hdr) with DDR3 training code +BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068 diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig new file mode 100644 index 0000000000..b72428555d --- /dev/null +++ b/configs/helios4_defconfig @@ -0,0 +1,58 @@ +CONFIG_ARM=y +CONFIG_ARCH_MVEBU=y +CONFIG_SYS_TEXT_BASE=0x00800000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_HELIOS4=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="armada-388-helios4" +CONFIG_DEBUG_UART=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTDELAY=3 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x141 +CONFIG_SPL_I2C_SUPPORT=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +# CONFIG_SPL_PARTITION_UUIDS is not set +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_MV=y +CONFIG_AHCI=y +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_GIGE=y +CONFIG_MVNETA=y +CONFIG_PCI=y +CONFIG_DEBUG_UART_BASE=0xd0012000 +CONFIG_DEBUG_UART_CLOCK=250000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_KIRKWOOD_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_STORAGE=y diff --git a/include/configs/helios4.h b/include/configs/helios4.h new file mode 100644 index 0000000000..5a4b7055fa --- /dev/null +++ b/include/configs/helios4.h @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Stefan Roese <sr@denx.de> + */ + +#ifndef _CONFIG_HELIOS4_H +#define _CONFIG_HELIOS4_H + +/* + * High Level Configuration Options (easy to change) + */ + +/* + * TEXT_BASE needs to be below 16MiB, since this area is scrubbed + * for DDR ECC byte filling in the SPL before loading the main + * U-Boot into it. + */ +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +/* + * Commands configuration + */ + +/* SPI NOR flash default params, used by sf commands */ +#define CONFIG_SF_DEFAULT_BUS 1 + +/* + * SDIO/MMC Card Configuration + */ +#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE + +/* USB/EHCI configuration */ +#define CONFIG_EHCI_IS_TDI + +#define CONFIG_ENV_MIN_ENTRIES 128 + +/* + * SATA/SCSI/AHCI configuration + */ +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 +#define CONFIG_SYS_SCSI_MAX_LUN 2 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +/* Environment in MMC */ +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SECT_SIZE 0x200 +#define CONFIG_ENV_SIZE 0x10000 +/* + * For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC + * boot image starts @ LBA-0. + * As result in MMC/eMMC case it will be a 1 sector gap between u-boot + * image and environment + */ +#define CONFIG_ENV_OFFSET 0xf0000 +#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET + +#define CONFIG_PHY_MARVELL /* there is a marvell phy */ +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ + +/* PCIe support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_PCI_MVEBU +#define CONFIG_PCI_SCAN_SHOW +#endif + +/* Keep device tree and initrd in lower memory so the kernel can access them */ +#define RELOCATION_LIMITS_ENV_SETTINGS \ + "fdt_high=0x10000000\0" \ + "initrd_high=0x10000000\0" + +/* SPL */ +/* + * Select the boot device here + * + * Currently supported are: + * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash + * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) + */ +#define SPL_BOOT_SPI_NOR_FLASH 1 +#define SPL_BOOT_SDIO_MMC_CARD 2 +#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SDIO_MMC_CARD + +/* Defines for SPL */ +#define CONFIG_SPL_SIZE (140 << 10) +#define CONFIG_SPL_TEXT_BASE 0x40000030 +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif + +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH +/* SPL related SPI defines */ +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS +#endif + +#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD +/* SPL related MMC defines */ +#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS +#ifdef CONFIG_SPL_BUILD +#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ +#endif + +/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ +#define CONFIG_SPD_EEPROM 0x4e +#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ + +#endif + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* Include the common distro boot environment */ +#ifndef CONFIG_SPL_BUILD + +#ifdef CONFIG_MMC +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#ifdef CONFIG_USB_STORAGE +#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_DEVICES_USB(func) +#endif + +#ifdef CONFIG_SATA +#define BOOT_TARGET_DEVICES_SATA(func) func(SATA, sata, 0) +#else +#define BOOT_TARGET_DEVICES_SATA(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_USB(func) \ + BOOT_TARGET_DEVICES_SATA(func) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#define KERNEL_ADDR_R __stringify(0x800000) +#define FDT_ADDR_R __stringify(0x100000) +#define RAMDISK_ADDR_R __stringify(0x1800000) +#define SCRIPT_ADDR_R __stringify(0x200000) +#define PXEFILE_ADDR_R __stringify(0x300000) + +#define LOAD_ADDRESS_ENV_SETTINGS \ + "kernel_addr_r=" KERNEL_ADDR_R "\0" \ + "fdt_addr_r=" FDT_ADDR_R "\0" \ + "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \ + "scriptaddr=" SCRIPT_ADDR_R "\0" \ + "pxefile_addr_r=" PXEFILE_ADDR_R "\0" + +#include <config_distro_bootcmd.h> + +#define CONFIG_EXTRA_ENV_SETTINGS \ + RELOCATION_LIMITS_ENV_SETTINGS \ + LOAD_ADDRESS_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "console=ttyS0,115200\0" \ + BOOTENV + +#endif /* CONFIG_SPL_BUILD */ + +#endif /* _CONFIG_HELIOS4_H */