diff mbox series

powerpc/powernv: copy/paste - Mask SO bit in CR

Message ID 20180604083338.2661-1-mpe@ellerman.id.au (mailing list archive)
State Accepted
Commit 75743649064ec0cf5ddd69f240ef23af66dde16e
Headers show
Series powerpc/powernv: copy/paste - Mask SO bit in CR | expand

Commit Message

Michael Ellerman June 4, 2018, 8:33 a.m. UTC
NX can set the 3rd bit in CR register for XER[SO] (Summary overflow)
which is not related to paste request. The current paste function
returns failure for a successful request when this bit is set. So mask
this bit and check the proper return status.

Fixes: 2392c8c8c045 ("powerpc/powernv/vas: Define copy/paste interfaces")
Cc: stable@vger.kernel.org # v4.14+
Signed-off-by: Haren Myneni <haren@us.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
---
 arch/powerpc/platforms/powernv/copy-paste.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Michael Ellerman June 5, 2018, 3:19 p.m. UTC | #1
On Mon, 2018-06-04 at 08:33:38 UTC, Michael Ellerman wrote:
> NX can set the 3rd bit in CR register for XER[SO] (Summary overflow)
> which is not related to paste request. The current paste function
> returns failure for a successful request when this bit is set. So mask
> this bit and check the proper return status.
> 
> Fixes: 2392c8c8c045 ("powerpc/powernv/vas: Define copy/paste interfaces")
> Cc: stable@vger.kernel.org # v4.14+
> Signed-off-by: Haren Myneni <haren@us.ibm.com>
> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

Applied to powerpc next.

https://git.kernel.org/powerpc/c/75743649064ec0cf5ddd69f240ef23

cheers
diff mbox series

Patch

diff --git a/arch/powerpc/platforms/powernv/copy-paste.h b/arch/powerpc/platforms/powernv/copy-paste.h
index 3fa62de96d9c..cb36f9fbcef3 100644
--- a/arch/powerpc/platforms/powernv/copy-paste.h
+++ b/arch/powerpc/platforms/powernv/copy-paste.h
@@ -41,5 +41,6 @@  static inline int vas_paste(void *paste_address, int offset)
 		: "b" (offset), "b" (paste_address)
 		: "memory", "cr0");
 
-	return (cr >> CR0_SHIFT) & CR0_MASK;
+	/* We mask with 0xE to ignore SO */
+	return (cr >> CR0_SHIFT) & 0xE;
 }