From patchwork Sun Jun 3 22:36:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 924772 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="CIVxkuYc"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40zXzg2l5dz9ryk for ; Mon, 4 Jun 2018 08:38:55 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751795AbeFCWia (ORCPT ); Sun, 3 Jun 2018 18:38:30 -0400 Received: from mail-lf0-f67.google.com ([209.85.215.67]:33885 "EHLO mail-lf0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751706AbeFCWiY (ORCPT ); Sun, 3 Jun 2018 18:38:24 -0400 Received: by mail-lf0-f67.google.com with SMTP id o9-v6so22254297lfk.1; Sun, 03 Jun 2018 15:38:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ASM6UGc3tjWV8yR28zPoHohRmblqfCz+RGQZb6C2Rps=; b=CIVxkuYcofwM+e6PT/Fgn39z3I4soS1O5Tlwq9CHyxbAzlUa3raHmEcKSDEUklo4+T 4PTDBZLPCaIo4C73vMcuEwMwGhkLbEfpbuEMJpJ6Q5xoViHnBi+FHg/xgqdJ4bvcSuqp t7N9It5dTyrrtq8vg4BwJ80M25+mUJgsUqZCm9+mag3KKDqSQeP/ilWf2aHvz1c3XyJI UqKrJ+dPispwp3jXlYO2lKJYSHLDLX0SWilqdFc56wUdpynM9XB7ZmUoXZjfwdD1HUk7 ZbfKGaFTosJUPBvs01Fg4ztbjq4Z36lTL07tOOEQ0EnQF7CTI02QotBLZlWM/vHcRFpC npGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ASM6UGc3tjWV8yR28zPoHohRmblqfCz+RGQZb6C2Rps=; b=aBsG1UpRTX4JThgG/EkY1icj0g2rbM9/ZxS/8NnvibehC9Rv63VcRMMPfrPaLWws4d qWg30Uo22J+a0q60GFT11yEj9QK9uickQJLqYkx1nHo7Vb82zIjn8/+Coy3wqWwsqln/ c5MMpmZNxsfaqhvUTueCTgrzbkBBTqfJMvh66oqJ9QVMVBzrn9rinxR+VwMIpw91M9UN 4+/e11x5AVz/wot0aqk+4rHRbG0HsOWlMgRYtrkkH7pZm4WbUpKCbIw6fh3wRPmA/Pde fhGmkte6FzGNqdXkCYibGOxzv4GIo+H9WyygW+7HjJQyyB57qaNxgZ6T8PfzfOmD+glY p+XA== X-Gm-Message-State: ALKqPwdwhxnf+ApjjEd2zHzVR1Mme7PkVt8JhcCqCtQcGV3jobkbj1dM n28ydEZoAFOQBHSIron2UMM= X-Google-Smtp-Source: ADUXVKIaD1x4E+bdXifbabUuCoYIy5SZKAlpvDu5zodrctJQ11ehu+iy9B5rh50R/wjwPqH0arjmzg== X-Received: by 2002:a2e:7113:: with SMTP id m19-v6mr14106978ljc.44.1528065502129; Sun, 03 Jun 2018 15:38:22 -0700 (PDT) Received: from localhost.localdomain (109-252-91-41.nat.spd-mgts.ru. [109.252.91.41]) by smtp.gmail.com with ESMTPSA id a2-v6sm9344121ljd.18.2018.06.03.15.38.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 03 Jun 2018 15:38:21 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Peter De Schrijver , Jonathan Hunter , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/5] clk: tegra20: Turn EMC clock gate into divider Date: Mon, 4 Jun 2018 01:36:52 +0300 Message-Id: <20180603223654.23324-4-digetx@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180603223654.23324-1-digetx@gmail.com> References: <20180603223654.23324-1-digetx@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Kernel should never gate the EMC clock as it causes immediate lockup, so removing clk-gate functionality doesn't affect anything. Turning EMC clk gate into divider allows to implement glitch-less EMC scaling, avoiding reparenting to a backup clock. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra20.c | 36 ++++++++++++++++++++++++--------- 1 file changed, 26 insertions(+), 10 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index cc857d4d4a86..2bd35418716a 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -578,7 +578,6 @@ static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = { [tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true }, [tegra_clk_fuse] = { .dt_id = TEGRA20_CLK_FUSE, .present = true }, [tegra_clk_kfuse] = { .dt_id = TEGRA20_CLK_KFUSE, .present = true }, - [tegra_clk_emc] = { .dt_id = TEGRA20_CLK_EMC, .present = true }, }; static unsigned long tegra20_clk_measure_input_freq(void) @@ -799,6 +798,31 @@ static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { TEGRA_INIT_DATA_NODIV("disp2", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, TEGRA20_CLK_DISP2), }; +static void __init tegra20_emc_clk_init(void) +{ + struct clk *clk; + + clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, + ARRAY_SIZE(mux_pllmcp_clkm), + CLK_SET_RATE_NO_REPARENT, + clk_base + CLK_SOURCE_EMC, + 30, 2, 0, &emc_lock); + + clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, + &emc_lock); + clks[TEGRA20_CLK_MC] = clk; + + /* + * Note that 'emc_mux' source and 'emc' rate shouldn't be changed at + * the same time due to a HW bug, this won't happen because we're + * defining 'emc_mux' and 'emc' as a distinct clocks. + */ + clk = clk_register_divider(NULL, "emc", "emc_mux", CLK_IS_CRITICAL, + clk_base + CLK_SOURCE_EMC, 0, 7, + 0, &emc_lock); + clks[TEGRA20_CLK_EMC] = clk; +} + static void __init tegra20_periph_clk_init(void) { struct tegra_periph_init_data *data; @@ -812,15 +836,7 @@ static void __init tegra20_periph_clk_init(void) clks[TEGRA20_CLK_AC97] = clk; /* emc */ - clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, - ARRAY_SIZE(mux_pllmcp_clkm), - CLK_SET_RATE_NO_REPARENT, - clk_base + CLK_SOURCE_EMC, - 30, 2, 0, &emc_lock); - - clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, - &emc_lock); - clks[TEGRA20_CLK_MC] = clk; + tegra20_emc_clk_init(); /* dsi */ clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,