From patchwork Sat Jun 2 09:20:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhadram Varka X-Patchwork-Id: 924449 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40ybKV5v5Xz9ry1 for ; Sat, 2 Jun 2018 19:21:02 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751099AbeFBJVB (ORCPT ); Sat, 2 Jun 2018 05:21:01 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:11576 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750821AbeFBJVA (ORCPT ); Sat, 2 Jun 2018 05:21:00 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Sat, 02 Jun 2018 02:20:56 -0700 Received: from HQMAIL107.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sat, 02 Jun 2018 02:21:00 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sat, 02 Jun 2018 02:21:00 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Sat, 2 Jun 2018 09:20:54 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Sat, 2 Jun 2018 09:20:54 +0000 Received: from vbhadram.nvidia.com (Not Verified[10.19.65.141]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sat, 02 Jun 2018 02:20:54 -0700 From: Bhadram Varka To: , , , , , CC: , , Subject: [PATCH V2 1/3] arm64: tegra: Remove unused interrupt properties Date: Sat, 2 Jun 2018 14:50:49 +0530 Message-ID: <1527931251-4809-1-git-send-email-vbhadram@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org DWC EQOS on Tegra handles all interrupts through common interrupt line. So lets remove unused power and per-channel interrupt properties. Signed-off-by: Bhadram Varka --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index b762227..252133b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -41,16 +41,7 @@ compatible = "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"; reg = <0x0 0x02490000 0x0 0x10000>; - interrupts = , /* common */ - , /* power */ - , /* rx0 */ - , /* tx0 */ - , /* rx1 */ - , /* tx1 */ - , /* rx2 */ - , /* tx2 */ - , /* rx3 */ - ; /* tx3 */ + interrupts = ; /* common */ clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, <&bpmp TEGRA186_CLK_EQOS_AXI>, <&bpmp TEGRA186_CLK_EQOS_RX>,