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[83.42.150.173]) by smtp.gmail.com with ESMTPSA id z63-v6sm62208146wrb.34.2018.06.02.00.30.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 02 Jun 2018 00:30:15 -0700 (PDT) From: Sergio Paracuellos To: linus.walleij@linaro.org Cc: robh+dt@kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, gregkh@linuxfoundation.org, neil@brown.name, driverdev-devel@linuxdriverproject.org Subject: [PATCH 2/2] dt-bindings: document gpio-mt7621 bindings Date: Sat, 2 Jun 2018 09:30:10 +0200 Message-Id: <1527924610-13135-3-git-send-email-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1527924610-13135-1-git-send-email-sergio.paracuellos@gmail.com> References: <1527924610-13135-1-git-send-email-sergio.paracuellos@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add a devicetree binding documentation for the mt7621 driver. Signed-off-by: Sergio Paracuellos Reviewed-by: NeilBrown --- .../bindings/gpio/mediatek,mt7621-gpio.txt | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/mediatek,mt7621-gpio.txt diff --git a/Documentation/devicetree/bindings/gpio/mediatek,mt7621-gpio.txt b/Documentation/devicetree/bindings/gpio/mediatek,mt7621-gpio.txt new file mode 100644 index 0000000..30d8a02 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/mediatek,mt7621-gpio.txt @@ -0,0 +1,68 @@ +Mediatek SoC GPIO controller bindings + +The IP core used inside these SoCs has 3 banks of 32 GPIOs each. +The registers of all the banks are interwoven inside one single IO range. +We load one GPIO controller instance per bank. To make this possible +we support 2 types of nodes. The parent node defines the memory I/O range and +has 3 children each describing a single bank. Also the GPIO controller can receive +interrupts on any of the GPIOs, either edge or level. It then interrupts the CPU +using GIC INT12. + +Required properties for the top level node: +- compatible: + - "mediatek,mt7621-gpio" for Mediatek controllers +- reg : Physical base address and length of the controller's registers +- interrupt-parent : phandle of the parent interrupt controller. +- interrupts : Interrupt specifier for the controllers interrupt. +- interrupt-controller : Mark the device node as an interrupt controller. +- #interrupt-cells : Should be 2. The first cell defines the interrupt number. + The second cell bits[3:0] is used to specify trigger type as follows: + - 1 = low-to-high edge triggered. + - 2 = high-to-low edge triggered. + - 4 = active high level-sensitive. + - 8 = active low level-sensitive. + + +Required properties for the GPIO bank node: +- compatible: + - "mediatek,mt7621-gpio-bank" for Mediatek banks +- #gpio-cells : Should be two. The first cell is the GPIO pin number and the + second cell specifies GPIO flags, as defined in . + Only the GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported. +- gpio-controller : Marks the device node as a GPIO controller. +- reg : The id of the bank that the node describes. + +Example: + gpio@600 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "mediatek,mt7621-gpio"; + reg = <0x600 0x100>; + + interrupt-parent = <&gic>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + + gpio0: bank@0 { + reg = <0>; + compatible = "mediatek,mt7621-gpio-bank"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio1: bank@1 { + reg = <1>; + compatible = "mediatek,mt7621-gpio-bank"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio2: bank@2 { + reg = <2>; + compatible = "mediatek,mt7621-gpio-bank"; + gpio-controller; + #gpio-cells = <2>; + }; + };