| Message ID | f95da1eb3e434552a0634d709a7e041a@mips.com |
|---|---|
| State | New |
| Headers | show |
| Series | MIPS: Add support for -mcrc and -mginv options | expand |
Robert Suchanek <Robert.Suchanek@mips.com> writes: > This patch adds -mcrc and -mginv options to pass through them > to the assembler. > > Regards, > Robert > > gcc/ChangeLog: > > 2018-06-01 Matthew Fortune <matthew.fortune@mips.com> > > * config/mips/mips.h (ASM_SPEC): Pass through -mcrc, -mno-crc, > -mginv and -mno-ginv to the assembler. > * config/mips/mips.opt (-mcrc): New option. > (-mginv): Likewise. > * doc/invoke.text (-mcrc): Document. > (-mginv): Likewise. The patch is OK but should probably wait until the binutils support is committed. I see CRC ASE support in discussion up until: https://sourceware.org/ml/binutils/2017-12/msg00069.html And GINV support up to: https://sourceware.org/ml/binutils/2018-01/msg00125.html Thanks, Matthew
Robert Suchanek <Robert.Suchanek@mips.com> writes: > This patch adds -mcrc and -mginv options to pass through them > to the assembler. > > Regards, > Robert > > gcc/ChangeLog: > > 2018-06-01 Matthew Fortune <matthew.fortune@mips.com> > > * config/mips/mips.h (ASM_SPEC): Pass through -mcrc, -mno-crc, > -mginv and -mno-ginv to the assembler. > * config/mips/mips.opt (-mcrc): New option. > (-mginv): Likewise. > * doc/invoke.text (-mcrc): Document. > (-mginv): Likewise. Since CRC and GINV ASEs have now been committed to binutils, please go ahead with this change. Thanks, Matthew
Hi, > Since CRC and GINV ASEs have now been committed to binutils, please go > ahead with this change. This is now committed as r261635. Robert
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index f290560..13c30f0 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1354,6 +1354,8 @@ struct mips_cpu_info { %{meva} %{mno-eva} \ %{mvirt} %{mno-virt} \ %{mxpa} %{mno-xpa} \ +%{mcrc} %{mno-crc} \ +%{mginv} %{mno-ginv} \ %{mmsa} %{mno-msa} \ %{msmartmips} %{mno-smartmips} \ %{mmt} %{mno-mt} \ diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index 545da54..5a9f255 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -412,6 +412,14 @@ mxpa Target Report Var(TARGET_XPA) Use eXtended Physical Address (XPA) instructions. +mcrc +Target Report Var(TARGET_CRC) +Use Cyclic Redundancy Check (CRC) instructions. + +mginv +Target Report Var(TARGET_GINV) +Use Global INValidate (GINV) instructions. + mvr4130-align Target Report Mask(VR4130_ALIGN) Perform VR4130-specific alignment optimizations. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 53ef14c..bcb4c14 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -888,6 +888,8 @@ Objective-C and Objective-C++ Dialects}. -meva -mno-eva @gol -mvirt -mno-virt @gol -mxpa -mno-xpa @gol +-mcrc -mno-crc @gol +-mginv -mno-ginv @gol -mmicromips -mno-micromips @gol -mmsa -mno-msa @gol -mfpu=@var{fpu-type} @gol @@ -20701,6 +20703,18 @@ Use (do not use) the MIPS Virtualization (VZ) instructions. @opindex mno-xpa Use (do not use) the MIPS eXtended Physical Address (XPA) instructions. +@item -mcrc +@itemx -mno-crc +@opindex mcrc +@opindex mno-crc +Use (do not use) the MIPS Cyclic Redundancy Check (CRC) instructions. + +@item -mginv +@itemx -mno-ginv +@opindex mginv +@opindex mno-ginv +Use (do not use) the MIPS Global INValidate (GINV) instructions. + @item -mlong64 @opindex mlong64 Force @code{long} types to be 64 bits wide. See @option{-mlong32} for