[rs6000,3/9] Testcase coverage for vec_vsx_ld() instrinsics

Message ID	1527796668.15912.27.camel@brimstone.rchland.ibm.com
State	New
Headers	show Return-Path: <gcc-patches-return-478864-incoming=patchwork.ozlabs.org@gcc.gnu.org> DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:reply-to:to:cc:in-reply-to:references:content-type :date:mime-version:content-transfer-encoding:message-id; q=dns; s=default; b=YvcENZPQbZdaeq4+/XeE721Z79ZMAiOG7734ThVeDBUm69lHf1 ed2o1HZYgwzOKYiQ6R8Byy1zlptYlLoBYpyXGW0WbE0uJTuFnrEd5lq9d7B+iXTy MFdS6lUdxSRH0hAk+AY6FOUYgWZbA6fk1uuLkCJiSdafS0AD3WILvbASo= Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk Sender: gcc-patches-owner@gcc.gnu.org Gateway: Authorized Use Only! Violators will be prosecuted for <gcc-patches@gcc.gnu.org> from <will_schmidt@vnet.ibm.com>; Thu, 31 May 2018 13:57:52 -0600 Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 31 May 2018 13:57:50 -0600 Subject: [PATCH, rs6000 3/9] Testcase coverage for vec_vsx_ld() instrinsics From: Will Schmidt <will_schmidt@vnet.ibm.com> Reply-To: will_schmidt@vnet.ibm.com To: Segher Boessenkool <segher@kernel.crashing.org> Cc: Bill Schmidt <wschmidt@linux.vnet.ibm.com>, David Edelsohn <dje.gcc@gmail.com>, GCC Patches <gcc-patches@gcc.gnu.org> In-Reply-To: <1527794851.6620.20.camel@brimstone.rchland.ibm.com> References: <1527794851.6620.20.camel@brimstone.rchland.ibm.com> Content-Type: text/plain; charset="UTF-8" Date: Thu, 31 May 2018 14:57:48 -0500 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Message-Id: <1527796668.15912.27.camel@brimstone.rchland.ibm.com>
Series	gimple folding of vector loads/stores + tests \| expand [rs6000,0/9] gimple folding of vector loads/stores + tests [rs6000,1/9] Testcase coverage for vec_xl() instrinsics [rs6000,2/9] Testcase coverage for builtin_vec_xl() instrinsics [rs6000,3/9] Testcase coverage for vec_vsx_ld() instrinsics [rs6000,4/9] Testcase coverage for vec_xst() instrinsics [rs6000,5/9] Testcase coverage for builtin_vec_xst() instrinsics [rs6000,6/9] Testcase coverage for vec_vsx_st() intrinsics [rs6000,7/9] testcase updates for unaligned loads/stores [rs6000,8/9] enable gimple folding for vec_xl, vec_xst [rs6000,9/9] Enable some additional combinations for builtin_vec_xst

diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c new file mode 100644 index 0000000..19b0968 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c @@ -0,0 +1,38 @@ +/* Verify that overloaded built-ins for vec_vsx_ld* with char + inputs produce the right code. */ + +/* { dg-do compile { target { powerpc*-*-linux* } } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ + +#include <altivec.h> +#define BUILD_VAR_TEST(TESTNAME1, RETTYPE, VAR_OFFSET, LOADFROM) \ +RETTYPE \ +TESTNAME1 ## _var (VAR_OFFSET offset, LOADFROM * loadfrom) \ +{ \ + return vec_vsx_ld (offset, loadfrom); \ +} + +#define BUILD_CST_TEST(TESTNAME1, RETTYPE, CST_OFFSET, LOADFROM) \ +RETTYPE \ +TESTNAME1 ## _cst (LOADFROM * loadfrom) \ +{ \ + return vec_vsx_ld (CST_OFFSET, loadfrom); \ +} + +BUILD_VAR_TEST( test1, vector signed char, signed long long, signed char); +BUILD_VAR_TEST( test2, vector signed char, signed int, signed char); +BUILD_CST_TEST( test3, vector signed char, 12, signed char); +BUILD_VAR_TEST( test4, vector unsigned char, signed long long, unsigned char); +BUILD_VAR_TEST( test5, vector unsigned char, signed int, unsigned char); +BUILD_CST_TEST( test6, vector unsigned char, 12, unsigned char); + +BUILD_VAR_TEST( test7, vector signed char, signed long long, vector signed char); +BUILD_VAR_TEST( test8, vector signed char, signed int, vector signed char); +BUILD_CST_TEST( test9, vector signed char, 12, vector signed char); +BUILD_VAR_TEST( test10, vector unsigned char, signed long long, vector unsigned char); +BUILD_VAR_TEST( test11, vector unsigned char, signed int, vector unsigned char); +BUILD_CST_TEST( test12, vector unsigned char, 12, vector unsigned char); + +/* { dg-final { scan-assembler-times "lxvw4x|lxvd2x|lxvx|lvx" 12 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c new file mode 100644 index 0000000..f01d0bd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c @@ -0,0 +1,31 @@ +/* Verify that overloaded built-ins for vec_vsx_ld* with double + inputs produce the right code. */ + +/* { dg-do compile { target { powerpc*-*-linux* } } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ + +#include <altivec.h> +#define BUILD_VAR_TEST(TESTNAME1, RETTYPE, VAR_OFFSET, LOADFROM) \ +RETTYPE \ +TESTNAME1 ## _var (VAR_OFFSET offset, LOADFROM * loadfrom) \ +{ \ + return vec_vsx_ld (offset, loadfrom); \ +} + +#define BUILD_CST_TEST(TESTNAME1, RETTYPE, CST_OFFSET, LOADFROM) \ +RETTYPE \ +TESTNAME1 ## _cst (LOADFROM * loadfrom) \ +{ \ + return vec_vsx_ld (CST_OFFSET, loadfrom); \ +} + +BUILD_VAR_TEST( test1, vector double, long long, double); +BUILD_VAR_TEST( test2, vector double, int, double); +BUILD_CST_TEST( test3, vector double, 12, double); + +BUILD_VAR_TEST( test4, vector double, int, vector double); +BUILD_VAR_TEST( test5, vector double, long long, vector double); +BUILD_CST_TEST( test6, vector double, 12, vector double); + +/* { dg-final { scan-assembler-times "lxvd2x|lxvx|lvx" 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c new file mode 100644 index 0000000..8236d8b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c @@ -0,0 +1,31 @@ +/* Verify that overloaded built-ins for vec_vsx_ld with float + inputs produce the right code. */ + +/* { dg-do compile { target { powerpc*-*-linux* } } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ + +#include <altivec.h> +#define BUILD_VAR_TEST(TESTNAME1, RETTYPE, VAR_OFFSET, LOADFROM) \ +RETTYPE \ +TESTNAME1 ## _var (VAR_OFFSET offset, LOADFROM * loadfrom) \ +{ \ + return vec_vsx_ld (offset, loadfrom); \ +} + +#define BUILD_CST_TEST(TESTNAME1, RETTYPE, CST_OFFSET, LOADFROM) \ +RETTYPE \ +TESTNAME1 ## _cst (LOADFROM * loadfrom) \ +{ \ + return vec_vsx_ld (CST_OFFSET, loadfrom); \ +} + +BUILD_VAR_TEST( test1, vector float, signed long long, float); +BUILD_VAR_TEST( test3, vector float, signed int, float); +BUILD_CST_TEST( test4, vector float, 12, float); + +BUILD_VAR_TEST( test5, vector float, signed long long, vector float); +BUILD_VAR_TEST( test7, vector float, signed int, vector float); +BUILD_CST_TEST( test8, vector float, 12, vector float); + +/* { dg-final { scan-assembler-times "lxvw4x|lxvd2x|lxvx|lvx" 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c new file mode 100644 index 0000000..70033e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c @@ -0,0 +1,37 @@ +/* Verify that overloaded built-ins for vec_vsx_ld with int + inputs produce the right code. */ + +/* { dg-do compile { target { powerpc*-*-linux* } } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ + +#include <altivec.h> +#define BUILD_VAR_TEST(TESTNAME1, RETTYPE, VAR_OFFSET, LOADFROM) \ +RETTYPE \ +TESTNAME1 ## _var (VAR_OFFSET offset, LOADFROM * loadfrom) \ +{ \ + return vec_vsx_ld (offset, loadfrom); \ +} + +#define BUILD_CST_TEST(TESTNAME1, RETTYPE, CST_OFFSET, LOADFROM) \ +RETTYPE \ +TESTNAME1 ## _cst (LOADFROM * loadfrom) \ +{ \ + return vec_vsx_ld (CST_OFFSET, loadfrom); \ +} + +BUILD_VAR_TEST( test1, vector signed int, signed long long, signed int); +BUILD_VAR_TEST( test2, vector signed int, signed int, signed int); +BUILD_CST_TEST( test3, vector signed int, 12, signed int); +BUILD_VAR_TEST( test4, vector unsigned int, signed long long, unsigned int); +BUILD_VAR_TEST( test5, vector unsigned int, signed int, unsigned int); +BUILD_CST_TEST( test6, vector unsigned int, 12, unsigned int); + +BUILD_VAR_TEST( test7, vector signed int, signed long long, vector signed int); +BUILD_VAR_TEST( test8, vector signed int, signed int, vector signed int); +BUILD_CST_TEST( test9, vector signed int, 12, vector signed int); +BUILD_VAR_TEST( test10, vector unsigned int, signed long long, vector unsigned int); +BUILD_VAR_TEST( test11, vector unsigned int, signed int, vector unsigned int); +BUILD_CST_TEST( test12, vector unsigned int, 12, vector unsigned int); + +/* { dg-final { scan-assembler-times "lxvw4x|lxvd2x|lxvx|lvx" 12 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c new file mode 100644 index 0000000..7df8340 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c @@ -0,0 +1,37 @@ +/* Verify that overloaded built-ins for vec_vsx_ld with long long + inputs produce the right code. */ + +/* { dg-do compile { target { powerpc*-*-linux* } } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ + +#include <altivec.h> +#define BUILD_VAR_TEST(TESTNAME1, RETTYPE, VAR_OFFSET, LOADFROM) \ +RETTYPE \ +TESTNAME1 ## _var (VAR_OFFSET offset, LOADFROM * loadfrom) \ +{ \ + return vec_vsx_ld (offset, loadfrom); \ +} + +#define BUILD_CST_TEST(TESTNAME1, RETTYPE, CST_OFFSET, LOADFROM) \ +RETTYPE \ +TESTNAME1 ## _cst (LOADFROM * loadfrom) \ +{ \ + return vec_vsx_ld (CST_OFFSET, loadfrom); \ +} + +BUILD_VAR_TEST( test1, vector signed long long, signed long long, signed long long); +BUILD_VAR_TEST( test2, vector signed long long, signed int, signed long long); +BUILD_CST_TEST( test3, vector signed long long, 12, signed long long); +BUILD_VAR_TEST( test4, vector unsigned long long, signed long long, unsigned long long); +BUILD_VAR_TEST( test5, vector unsigned long long, signed int, unsigned long long); +BUILD_CST_TEST( test6, vector unsigned long long, 12, unsigned long long); + +BUILD_VAR_TEST( test7, vector signed long long, signed long long, vector signed long long); +BUILD_VAR_TEST( test8, vector signed long long, signed int, vector signed long long); +BUILD_CST_TEST( test9, vector signed long long, 12, vector signed long long); +BUILD_VAR_TEST( test10, vector unsigned long long, signed long long, vector unsigned long long); +BUILD_VAR_TEST( test11, vector unsigned long long, signed int, vector unsigned long long); +BUILD_CST_TEST( test12, vector unsigned long long, 12, vector unsigned long long); + +/* { dg-final { scan-assembler-times "lxvd2x|lxvx|lvx" 12 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c new file mode 100644 index 0000000..031d03a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c @@ -0,0 +1,37 @@ +/* Verify that overloaded built-ins for vec_vsx_ld with short + inputs produce the right code. */ + +/* { dg-do compile { target { powerpc*-*-linux* } } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ + +#include <altivec.h> +#define BUILD_VAR_TEST(TESTNAME1, RETTYPE, VAR_OFFSET, LOADFROM) \ +RETTYPE \ +TESTNAME1 ## _var (VAR_OFFSET offset, LOADFROM * loadfrom) \ +{ \ + return vec_vsx_ld (offset, loadfrom); \ +} + +#define BUILD_CST_TEST(TESTNAME1, RETTYPE, CST_OFFSET, LOADFROM) \ +RETTYPE \ +TESTNAME1 ## _cst (LOADFROM * loadfrom) \ +{ \ + return vec_vsx_ld (CST_OFFSET, loadfrom); \ +} + +BUILD_VAR_TEST( test1, vector signed short, signed long long, signed short); +BUILD_VAR_TEST( test2, vector signed short, signed int, signed short); +BUILD_CST_TEST( test3, vector signed short, 12, signed short); +BUILD_VAR_TEST( test4, vector unsigned short, signed long long, unsigned short); +BUILD_VAR_TEST( test5, vector unsigned short, signed int, unsigned short); +BUILD_CST_TEST( test6, vector unsigned short, 12, unsigned short); + +BUILD_VAR_TEST( test7, vector signed short, signed long long, vector signed short); +BUILD_VAR_TEST( test8, vector signed short, signed int, vector signed short); +BUILD_CST_TEST( test9, vector signed short, 12, vector signed short); +BUILD_VAR_TEST( test10, vector unsigned short, signed long long, vector unsigned short); +BUILD_VAR_TEST( test11, vector unsigned short, signed int, vector unsigned short); +BUILD_CST_TEST( test12, vector unsigned short, 12, vector unsigned short); + +/* { dg-final { scan-assembler-times "lxvw4x|lxvd2x|lxvx|lvx" 12 } } */

[rs6000,3/9] Testcase coverage for vec_vsx_ld() instrinsics

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