Message ID | 20180530061740.31547-1-joel@jms.id.au |
---|---|
State | Accepted |
Headers | show |
Series | ARM: dts: aspeed: Fix hwrng register address | expand |
On Wed, May 30, 2018 at 03:47:40PM +0930, Joel Stanley wrote: > The register address should be the full address of the rng, not the > offset from the start of the SCU. > > Fixes: 5daa8212c08e ("ARM: dts: aspeed: Describe random number device") > Reviewed-by: Andrew Jeffery <andrew@aj.id.au> > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > Hi ARM maintainers, this was found when testing next-20180529 after the > merge of the aspeed 4.18 pull request. Can you please apply this one to > your -next tree? Certainly, applied to our next/dt branch now. Thanks, -Olof
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 5e947ed496c2..75df1573380e 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -145,9 +145,9 @@ }; - rng: hwrng@78 { + rng: hwrng@1e6e2078 { compatible = "timeriomem_rng"; - reg = <0x78 0x4>; + reg = <0x1e6e2078 0x4>; period = <1>; quality = <100>; }; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 24eec00c4a95..17f2714d18a7 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -189,9 +189,9 @@ }; }; - rng: hwrng@78 { + rng: hwrng@1e6e2078 { compatible = "timeriomem_rng"; - reg = <0x78 0x4>; + reg = <0x1e6e2078 0x4>; period = <1>; quality = <100>; };