| Message ID | 20180529163843.29608-1-marex@denx.de |
|---|---|
| State | Accepted |
| Commit | df78f016e84caede20938fb3e84acbb8ae7fc440 |
| Delegated to: | Marek Vasut |
| Headers | show |
| Series | [U-Boot] ARM: socfpga: Make DRAM node available in SPL | expand |
On Tue, 2018-05-29 at 18:38 +0200, Marek Vasut wrote: > The SPL can also parse the DRAM configuration node to figure out the > memory layout, make sure it is available. > > Signed-off-by: Marek Vasut <marex@denx.de> > Cc: Chin Liang See <chin.liang.see@intel.com> > Cc: Dinh Nguyen <dinguyen@kernel.org> > --- > arch/arm/dts/socfpga_arria10_socdk.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi > b/arch/arm/dts/socfpga_arria10_socdk.dtsi > index d7616dd1c5..3f59f02577 100644 > --- a/arch/arm/dts/socfpga_arria10_socdk.dtsi > +++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi > @@ -34,6 +34,7 @@ > name = "memory"; > device_type = "memory"; > reg = <0x0 0x40000000>; /* 1GB */ > + u-boot,dm-pre-reloc; > }; > > a10leds { Reviewed-by: Chin Liang See <chin.liang.see@intel.com> Thanks Chin Liang
diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi index d7616dd1c5..3f59f02577 100644 --- a/arch/arm/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi @@ -34,6 +34,7 @@ name = "memory"; device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ + u-boot,dm-pre-reloc; }; a10leds {
The SPL can also parse the DRAM configuration node to figure out the memory layout, make sure it is available. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> --- arch/arm/dts/socfpga_arria10_socdk.dtsi | 1 + 1 file changed, 1 insertion(+)