diff mbox series

[PULL,v1,05/38] target-microblaze: Correct special register array sizes

Message ID 20180529105011.1914-6-edgar.iglesias@gmail.com
State New
Headers show
Series Xilinx queue | expand

Commit Message

Edgar E. Iglesias May 29, 2018, 10:49 a.m. UTC 
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Correct special register array sizes.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/cpu.h       | 4 ++--
 target/microblaze/translate.c | 5 ++---
 2 files changed, 4 insertions(+), 5 deletions(-)
diff mbox series

Patch

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 5be71bc320..994496515f 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -242,8 +242,8 @@  struct CPUMBState {
     uint32_t bimm;
 
     uint32_t imm;
-    uint32_t regs[33];
-    uint32_t sregs[24];
+    uint32_t regs[32];
+    uint32_t sregs[14];
     float_status fp_status;
     /* Stack protectors. Yes, it's a hw feature.  */
     uint32_t slr, shr;
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 46595e6336..9614f15d58 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -54,7 +54,7 @@ 
 
 static TCGv env_debug;
 static TCGv cpu_R[32];
-static TCGv cpu_SR[18];
+static TCGv cpu_SR[14];
 static TCGv env_imm;
 static TCGv env_btaken;
 static TCGv env_btarget;
@@ -106,8 +106,7 @@  static const char *regnames[] =
 static const char *special_regnames[] =
 {
     "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
-    "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
-    "sr16", "sr17", "sr18"
+    "sr8", "sr9", "sr10", "sr11", "sr12", "sr13"
 };
 
 static inline void t_sync_flags(DisasContext *dc)