diff mbox series

[U-Boot,10/41] imx8: add basic cpu support

Message ID 20180528122526.20597-11-peng.fan@nxp.com
State Superseded
Delegated to: Stefano Babic
Headers show
Series imx: add i.MX8QXP support | expand

Commit Message

Peng Fan May 28, 2018, 12:24 p.m. UTC 
Add basic cpu support, including cpu revision, cpu type, cpu core
detection.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/arch-imx8/cpu.h | 26 ++++++++++++
 arch/arm/mach-imx/imx8/Makefile      |  1 +
 arch/arm/mach-imx/imx8/cpu.c         | 79 ++++++++++++++++++++++++++++++++++++
 3 files changed, 106 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-imx8/cpu.h
 create mode 100644 arch/arm/mach-imx/imx8/cpu.c
diff mbox series

Patch

diff --git a/arch/arm/include/asm/arch-imx8/cpu.h b/arch/arm/include/asm/arch-imx8/cpu.h
new file mode 100644
index 0000000000..9dfffc09bc
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/cpu.h
@@ -0,0 +1,26 @@ 
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#define MIDR_PARTNUM_CORTEX_A35 0xD04
+#define MIDR_PARTNUM_CORTEX_A53 0xD03
+#define MIDR_PARTNUM_CORTEX_A72 0xD08
+#define MIDR_PARTNUM_SHIFT 0x4
+#define MIDR_PARTNUM_MASK (0xFFF << 0x4)
+
+static inline unsigned int read_midr(void)
+{
+	unsigned long val;
+
+	asm volatile("mrs %0, midr_el1" : "=r" (val));
+
+	return val;
+}
+
+#define is_cortex_a35() (((read_midr() & MIDR_PARTNUM_MASK) >> \
+			 MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A35)
+#define is_cortex_a53() (((read_midr() & MIDR_PARTNUM_MASK) >> \
+			 MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A53)
+#define is_cortex_a72() (((read_midr() & MIDR_PARTNUM_MASK) >>\
+			 MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A72)
diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile
index 8ae0518c16..9545fd8d03 100644
--- a/arch/arm/mach-imx/imx8/Makefile
+++ b/arch/arm/mach-imx/imx8/Makefile
@@ -4,6 +4,7 @@ 
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+obj-y += cpu.o
 obj-y += fsl_mu_hal.o sci/ipc.o
 obj-y += sci/svc/misc/rpc_clnt.o
 obj-y += sci/svc/pad/rpc_clnt.o
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
new file mode 100644
index 0000000000..eed92d9963
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -0,0 +1,79 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch-imx/cpu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 get_cpu_rev(void)
+{
+	sc_ipc_t ipchndl;
+	u32 id = 0, rev = 0;
+	sc_err_t err;
+
+	ipchndl = gd->arch.ipc_channel_handle;
+
+	err = sc_misc_get_control(ipchndl, SC_R_SYSTEM, SC_C_ID, &id);
+	if (err != SC_ERR_NONE)
+		return 0;
+
+	rev = (id >> 5)  & 0xf;
+	id = (id & 0x1f) + MXC_SOC_IMX8;  /* Dummy ID for chip */
+
+	return (id << 12) | rev;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+const char *get_imx8_type(u32 imxtype)
+{
+	switch (imxtype) {
+	case MXC_CPU_IMX8QXP:
+		return "8QXP";
+	default:
+		return "??";
+	}
+}
+
+const char *get_imx8_rev(u32 rev)
+{
+	switch (rev) {
+	case CHIP_REV_A:
+		return "A";
+	case CHIP_REV_B:
+		return "B";
+	default:
+		return "?";
+	}
+}
+
+const char *get_core_name(void)
+{
+	if (is_cortex_a35())
+		return "A35";
+	else
+		return "?";
+}
+
+int print_cpuinfo(void)
+{
+	u32 cpurev;
+
+	cpurev = get_cpu_rev();
+
+	printf("CPU:   Freescale i.MX%s rev%s %s at %d MHz\n",
+	       get_imx8_type((cpurev & 0xFF000) >> 12),
+	       get_imx8_rev((cpurev & 0xFFF)),
+	       get_core_name(),
+	       mxc_get_clock(MXC_ARM_CLK) / 1000000);
+
+	return 0;
+}
+#endif