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[alpha] : Improve fix for PR83628

Message ID CAFULd4Z95WvG0sGGDTLBuiqnXb-e-+ibapi4WdoohDVeKe29nQ@mail.gmail.com
State New
Headers show
Series [alpha] : Improve fix for PR83628 | expand

Commit Message

Uros Bizjak May 25, 2018, 2:02 p.m. UTC 
Hello!

Attached patch improves fix for PR83628 by providing ashlsi3 pattern.
This allows combiner to remove subregs of inner DImode ashift.

2018-05-25  Uros Bizjak  <ubizjak@gmail.com>

    PR target/83628
    * config/alpha/alpha.md (ashlsi3): New insn pattern.
    (*ashlsi_se): Rename from *ashldi_se.  Define as sign
    extension of SImode operation.  Use const123_operand predicate.
    (*saddsi_1): Remove.
    (*saddl_se_1): Ditto.
    (*ssubsi_1): Ditto.
    (*ssubl_se_1): Ditto.
    * config/alpha/predicates.md (const123_operand): New predicate.
    * config/alpha/constraints.md (P): Use IN_RANGE.

Bootstrapped and regression tested on alphaev68-linux-gnu.

Committed to mainline SVN.

Uros.
diff mbox series

Patch

Index: alpha.md
===================================================================
--- alpha.md	(revision 260675)
+++ alpha.md	(working copy)
@@ -527,21 +527,6 @@ 
    s%P2add<modesuffix> %1,%3,%0
    s%P2sub<modesuffix> %1,%n3,%0")
 
-(define_insn_and_split "*saddsi_1"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(plus:SI
-	 (subreg:SI
-	  (ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
-		     (match_operand:DI 2 "const23_operand" "I,I")) 0)
-	 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
-  ""
-  "#"
-  ""
-  [(set (match_dup 0)
-	(plus:SI (ashift:SI (match_dup 1) (match_dup 2))
-		 (match_dup 3)))]
-  "operands[1] = gen_lowpart (SImode, operands[1]);")
-
 (define_insn "*saddl_se"
   [(set (match_operand:DI 0 "register_operand" "=r,r")
 	(sign_extend:DI
@@ -554,23 +539,6 @@ 
    s%P2addl %1,%3,%0
    s%P2subl %1,%n3,%0")
 
-(define_insn_and_split "*saddl_se_1"
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(sign_extend:DI
-	 (plus:SI
-	  (subreg:SI
-	   (ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
-		      (match_operand:DI 2 "const23_operand" "I,I")) 0)
-	 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
-  ""
-  "#"
-  ""
-  [(set (match_dup 0)
-	(sign_extend:DI
-	 (plus:SI (ashift:SI (match_dup 1) (match_dup 2))
-		  (match_dup 3))))]
-  "operands[1] = gen_lowpart (SImode, operands[1]);")
-
 (define_split
   [(set (match_operand:DI 0 "register_operand")
 	(sign_extend:DI
@@ -660,21 +628,6 @@ 
   ""
   "s%P2sub<modesuffix> %1,%3,%0")
 
-(define_insn_and_split "*ssubsi_1"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI
-	 (subreg:SI
-	  (ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
-		     (match_operand:DI 2 "const23_operand" "I")) 0)
-	 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
-  ""
-  "#"
-  ""
-  [(set (match_dup 0)
-	(minus:SI (ashift:SI (match_dup 1) (match_dup 2))
-		  (match_dup 3)))]
-  "operands[1] = gen_lowpart (SImode, operands[1]);")
-
 (define_insn "*ssubl_se"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(sign_extend:DI
@@ -685,23 +638,6 @@ 
   ""
   "s%P2subl %1,%3,%0")
 
-(define_insn_and_split "*ssubl_se_1"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(sign_extend:DI
-	 (minus:SI
-	  (subreg:SI
-	   (ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
-		      (match_operand:DI 2 "const23_operand" "I")) 0)
-	 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
-  ""
-  "#"
-  ""
-  [(set (match_dup 0)
-	(sign_extend:DI
-	 (minus:SI (ashift:SI (match_dup 1) (match_dup 2))
-		   (match_dup 3))))]
-  "operands[1] = gen_lowpart (SImode, operands[1]);")
-
 (define_insn "subv<mode>3"
   [(set (match_operand:I48MODE 0 "register_operand" "=r")
 	(minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ")
@@ -1260,13 +1196,25 @@ 
 }
   [(set_attr "type" "iadd,shift")])
 
-(define_insn "*ashldi_se"
+(define_insn "ashlsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(ashift:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
+		   (match_operand:SI 2 "const123_operand" "P")))]
+  ""
+{
+  if (operands[2] == const1_rtx)
+    return "addl %r1,%r1,%0";
+  else
+    return "s%P2addl %r1,0,%0";
+}
+  [(set_attr "type" "iadd")])
+
+(define_insn "*ashlsi_se"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(sign_extend:DI
-	 (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-			       (match_operand:DI 2 "const_int_operand" "P"))
-		    0)))]
-  "IN_RANGE (INTVAL (operands[2]), 1, 3)"
+	 (ashift:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
+		    (match_operand:SI 2 "const123_operand" "P"))))]
+  ""
 {
   if (operands[2] == const1_rtx)
     return "addl %r1,%r1,%0";
Index: constraints.md
===================================================================
--- constraints.md	(revision 260675)
+++ constraints.md	(working copy)
@@ -82,7 +82,7 @@ 
 (define_constraint "P"
   "The constant 1, 2 or 3"
   (and (match_code "const_int")
-       (match_test "ival == 1 || ival == 2 || ival == 3")))
+       (match_test "IN_RANGE (ival, 1, 3)")))
 
 ;; Floating-point constant constraints.
 (define_constraint "G"
Index: predicates.md
===================================================================
--- predicates.md	(revision 260675)
+++ predicates.md	(working copy)
@@ -74,6 +74,11 @@ 
   (and (match_code "const_int,const_wide_int,const_double,const_vector")
        (not (match_test "op == CONST0_RTX (mode)"))))
 
+;; Return 1 if OP is the constant 1, 2 or 3.
+(define_predicate "const123_operand"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (INTVAL (op), 1, 3)")))
+
 ;; Return 1 if OP is the constant 2 or 3.
 (define_predicate "const23_operand"
   (and (match_code "const_int")