| Message ID | 1527034517-7851-28-git-send-email-mjc@sifive.com |
|---|---|
| State | New |
| Headers | show |
| Series | QEMU 2.13 RISC-V updates | expand |
Le 23/05/2018 à 02:15, Michael Clark a écrit : > Refer to the RISC-V PSABI specification for details: > > - https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md > > Cc: Michael Tokarev <mjt@tls.msk.ru> > Cc: Laurent Vivier <laurent@vivier.eu> > Cc: Richard Henderson <richard.henderson@linaro.org> > Cc: Alistair Francis <Alistair.Francis@wdc.com> > Signed-off-by: Michael Clark <mjc@sifive.com> > --- > include/elf.h | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/include/elf.h b/include/elf.h > index 934dbbd6b3ae..d363ba85a688 100644 > --- a/include/elf.h > +++ b/include/elf.h > @@ -1285,6 +1285,14 @@ typedef struct { > #define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */ > #define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */ > > +/* RISC-V specific definitions. */ > +#define EF_RISCV_RVC 0x0001 > +#define EF_RISCV_FLOAT_ABI_SINGLE 0x0002 > +#define EF_RISCV_FLOAT_ABI_DOUBLE 0x0004 > +#define EF_RISCV_FLOAT_ABI_QUAD (0x0006 ^ Typo here -------------------------| Thanks, Laurent
On Wed, May 23, 2018 at 6:44 PM, Laurent Vivier <laurent@vivier.eu> wrote: > Le 23/05/2018 à 02:15, Michael Clark a écrit : > > Refer to the RISC-V PSABI specification for details: > > > > - https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md > > > > Cc: Michael Tokarev <mjt@tls.msk.ru> > > Cc: Laurent Vivier <laurent@vivier.eu> > > Cc: Richard Henderson <richard.henderson@linaro.org> > > Cc: Alistair Francis <Alistair.Francis@wdc.com> > > Signed-off-by: Michael Clark <mjc@sifive.com> > > --- > > include/elf.h | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/include/elf.h b/include/elf.h > > index 934dbbd6b3ae..d363ba85a688 100644 > > --- a/include/elf.h > > +++ b/include/elf.h > > @@ -1285,6 +1285,14 @@ typedef struct { > > #define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */ > > #define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), > imm22 */ > > > > +/* RISC-V specific definitions. */ > > +#define EF_RISCV_RVC 0x0001 > > +#define EF_RISCV_FLOAT_ABI_SINGLE 0x0002 > > +#define EF_RISCV_FLOAT_ABI_DOUBLE 0x0004 > > +#define EF_RISCV_FLOAT_ABI_QUAD (0x0006 > ^ > Typo here -------------------------| > Thanks! My mistake. The original patch had only EF_RISCV_RVE, which is the define we need for a subsequent patch, however I decided to add the remaining flags from the spec and indeed there was a paren in the spec. I'll respin this as a separate patch.
diff --git a/include/elf.h b/include/elf.h index 934dbbd6b3ae..d363ba85a688 100644 --- a/include/elf.h +++ b/include/elf.h @@ -1285,6 +1285,14 @@ typedef struct { #define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */ #define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */ +/* RISC-V specific definitions. */ +#define EF_RISCV_RVC 0x0001 +#define EF_RISCV_FLOAT_ABI_SINGLE 0x0002 +#define EF_RISCV_FLOAT_ABI_DOUBLE 0x0004 +#define EF_RISCV_FLOAT_ABI_QUAD (0x0006 +#define EF_RISCV_RVE 0x0008 +#define EF_RISCV_TSO 0x0010 + typedef struct elf32_rel { Elf32_Addr r_offset; Elf32_Word r_info;
Refer to the RISC-V PSABI specification for details: - https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md Cc: Michael Tokarev <mjt@tls.msk.ru> Cc: Laurent Vivier <laurent@vivier.eu> Cc: Richard Henderson <richard.henderson@linaro.org> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> --- include/elf.h | 8 ++++++++ 1 file changed, 8 insertions(+)