From patchwork Thu May 17 10:26:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrill Tkachov X-Patchwork-Id: 915310 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-477834-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=foss.arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="v0vvZhzm"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40mnYS4gxlz9s3c for ; Thu, 17 May 2018 20:27:24 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=wMJaf7Y7mkEOzOZP52fpZIFFt0i2e9bmCFE9SxGyezq W5Nq8DnB0xzpuWdtOSc/bC4Olq+ndIl7wwim1wcN69uF5YjHjiPzjIjmm6xTqhri BIl2LOzGMTXfT+enEdyvwHXReWm3yWWBxeLjiEhiIwFMqSxNNKIstUDhfSr/KG4o = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=W6CMFq8d3up+t1rntyOFB9wNHOg=; b=v0vvZhzm1l+ddVvIR Y5gJZndZlFXnxbOwtncSilCRflo9/eXKSaTn7+c94/FN5bg2T6xyO32GrJk6U7X3 GTftE9fTdLmZkpyVc5wwqGuN2VkVrGj1Nv5X9j4RDTCWMSCQGd3/8CCkNWj2slC2 mlalH92bAfcgrzffiyr48whwaU= Received: (qmail 61305 invoked by alias); 17 May 2018 10:27:01 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 61200 invoked by uid 89); 17 May 2018 10:27:00 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, KAM_SHORT autolearn=ham version=3.3.2 spammy=jb, simode, SImode, fp16 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 17 May 2018 10:26:56 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 50BD41529; Thu, 17 May 2018 03:26:55 -0700 (PDT) Received: from [10.2.207.77] (e100706-lin.cambridge.arm.com [10.2.207.77]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5955F3F25D; Thu, 17 May 2018 03:26:54 -0700 (PDT) Message-ID: <5AFD58EC.1080006@foss.arm.com> Date: Thu, 17 May 2018 11:26:52 +0100 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" CC: "Richard Earnshaw (lists)" , Ramana Radhakrishnan Subject: [PATCH][arm][2/2] Remove support for -march=armv3 and older Hi all, We deprecated architecture versions earlier than Armv4T in GCC 6 [1]. This patch removes support for architectures lower than Armv4. That is the -march values armv2, armv2a, armv3, armv3m are removed with this patch. I did not remove armv4 because it's a bit more involved code-wise and there has been some pushback on the implications for -mcpu=strongarm support. Removing armv3m and earlier though is pretty straightforward. This allows us to get rid of the armv3m and mode32 feature bits in arm-cpus.in as they can be assumed to be universally available. Consequently the mcpu values arm2, arm250, arm3, arm6, arm60, arm600, arm610, arm620, arm7, arm7d, arm7di, arm70, arm700, arm700i, arm710, arm720, arm710c, arm7100, arm7500, arm7500fe, arm7m, arm7dm, arm7dm are now also removed. Bootstrapped and tested on arm-none-linux-gnueabihf and on arm-none-eabi with an aprofile multilib configuration (which builds quite a lot of library configurations). Ramana, Richard, I'd appreciate an ok from either of you that you're happy for this to go ahead. Thanks, Kyrill [1] https://gcc.gnu.org/gcc-6/changes.html#arm 2018-05-17 Kyrylo Tkachov * config/arm/arm-cpus.in (armv3m, mode32): Delete features. (ARMv4): Update. (ARMv2, ARMv3, ARMv3m): Delete fgroups. (ARMv6m): Update. (armv2, armv2a, armv3, armv3m): Delete architectures. (arm2, arm250, arm3, arm6, arm60, arm600, arm610, arm620, arm7, arm7d, arm7di, arm70, arm700, arm700i, arm710, arm720, arm710c, arm7100, arm7500, arm7500fe, arm7m, arm7dm, arm7dmi): Delete cpus. * config/arm/arm.md (maddsidi4): Remove check for arm_arch3m. (*mulsidi3adddi): Likewise. (mulsidi3): Likewise. (*mulsidi3_nov6): Likewise. (umulsidi3): Likewise. (umulsidi3_nov6): Likewise. (umaddsidi4): Likewise. (*umulsidi3adddi): Likewise. (smulsi3_highpart): Likewise. (*smulsi3_highpart_nov6): Likewise. (umulsi3_highpart): Likewise. (*umulsi3_highpart_nov6): Likewise. * config/arm/arm.h (arm_arch3m): Delete. * config/arm/arm.c (arm_arch3m): Delete. (arm_option_override_internal): Update armv3-related comment. (arm_configure_build_target): Delete use of isa_bit_mode32. (arm_option_reconfigure_globals): Delete set of arm_ach3m. (arm_rtx_costs_internal): Delete check of arm_arch3m. * config/arm/arm-fixed.md (mulsq3): Delete check for arm_arch3m. (mulsa3): Likewise. (mulusa3): Likewise. * config/arm/arm-protos.h (arm_arch3m): Delete. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Likewise. * config/arm/t-arm-elf (all_early_nofp): Delete mentions of deleted architectures. 2018-05-17 Kyrylo Tkachov * gcc.target/arm/pr62554.c: Delete. * gcc.target/arm/pr69610-1.c: Likewise. * gcc.target/arm/pr69610-2.c: Likewise. diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 0a318877f10394e2c045d2a03a8f0757557136cf..16a381c86b6a7947e424b29fe67812990519ada9 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -48,15 +48,9 @@ # Features - general convention: all lower case. -# Extended multiply -define feature armv3m - # 26-bit mode support define feature mode26 -# 32-bit mode support -define feature mode32 - # Architecture rel 4 define feature armv4 @@ -215,10 +209,7 @@ define fgroup ALL_FPU_INTERNAL vfpv2 vfpv3 vfpv4 fpv5 fp16conv fp_dbl ALL_SIMD_I # -mfpu support. define fgroup ALL_FP fp16 ALL_FPU_INTERNAL -define fgroup ARMv2 notm -define fgroup ARMv3 ARMv2 mode32 -define fgroup ARMv3m ARMv3 armv3m -define fgroup ARMv4 ARMv3m armv4 +define fgroup ARMv4 armv4 notm define fgroup ARMv4t ARMv4 thumb define fgroup ARMv5t ARMv4t armv5t define fgroup ARMv5te ARMv5t armv5te @@ -232,7 +223,7 @@ define fgroup ARMv6zk ARMv6k define fgroup ARMv6t2 ARMv6 thumb2 # This is suspect. ARMv6-m doesn't really pull in any useful features # from ARMv5* or ARMv6. -define fgroup ARMv6m mode32 armv3m armv4 thumb armv5t armv5te armv6 be8 +define fgroup ARMv6m armv4 thumb armv5t armv5te armv6 be8 # This is suspect, the 'common' ARMv7 subset excludes the thumb2 'DSP' and # integer SIMD instructions that are in ARMv6T2. */ define fgroup ARMv7 ARMv6m thumb2 armv7 @@ -279,34 +270,6 @@ define fgroup ALL_QUIRKS quirk_no_volatile_ce quirk_armv6kz quirk_cm3_ldrd # end arch # -begin arch armv2 - tune for arm2 - tune flags CO_PROC NO_MODE32 - base 2 - isa ARMv2 mode26 -end arch armv2 - -begin arch armv2a - tune for arm2 - tune flags CO_PROC NO_MODE32 - base 2 - isa ARMv2 mode26 -end arch armv2a - -begin arch armv3 - tune for arm6 - tune flags CO_PROC - base 3 - isa ARMv3 mode26 -end arch armv3 - -begin arch armv3m - tune for arm7m - tune flags CO_PROC - base 3M - isa ARMv3m mode26 -end arch armv3m - begin arch armv4 tune for arm7tdmi tune flags CO_PROC @@ -675,154 +638,6 @@ end arch iwmmxt2 # option must similarly have a distinct feature set. Option aliases can be # added with the optalias statement -# V2/V2A Architecture Processors -begin cpu arm2 - tune flags CO_PROC NO_MODE32 - architecture armv2 - costs slowmul -end cpu arm2 - -begin cpu arm250 - tune flags CO_PROC NO_MODE32 - architecture armv2 - costs slowmul -end cpu arm250 - -begin cpu arm3 - tune flags CO_PROC NO_MODE32 - architecture armv2 - costs slowmul -end cpu arm3 - - -# V3 Architecture Processors -begin cpu arm6 - tune flags CO_PROC - architecture armv3 - costs slowmul -end cpu arm6 - -begin cpu arm60 - tune flags CO_PROC - architecture armv3 - costs slowmul -end cpu arm60 - -begin cpu arm600 - tune flags CO_PROC WBUF - architecture armv3 - costs slowmul -end cpu arm600 - -begin cpu arm610 - tune flags WBUF - architecture armv3 - costs slowmul -end cpu arm610 - -begin cpu arm620 - tune flags CO_PROC WBUF - architecture armv3 - costs slowmul -end cpu arm620 - -begin cpu arm7 - tune flags CO_PROC - architecture armv3 - costs slowmul -end cpu arm7 - -begin cpu arm7d - tune flags CO_PROC - architecture armv3 - costs slowmul -end cpu arm7d - -begin cpu arm7di - tune flags CO_PROC - architecture armv3 - costs slowmul -end cpu arm7di - -begin cpu arm70 - tune flags CO_PROC - architecture armv3 - costs slowmul -end cpu arm70 - -begin cpu arm700 - tune flags CO_PROC WBUF - architecture armv3 - costs slowmul -end cpu arm700 - -begin cpu arm700i - tune flags CO_PROC WBUF - architecture armv3 - costs slowmul -end cpu arm700i - -begin cpu arm710 - tune flags WBUF - architecture armv3 - costs slowmul -end cpu arm710 - -begin cpu arm720 - tune flags WBUF - architecture armv3 - costs slowmul -end cpu arm720 - -begin cpu arm710c - tune flags WBUF - architecture armv3 - costs slowmul -end cpu arm710c - -begin cpu arm7100 - tune flags WBUF - architecture armv3 - costs slowmul -end cpu arm7100 - -begin cpu arm7500 - tune flags WBUF - architecture armv3 - costs slowmul -end cpu arm7500 - -# Doesn't have an external co-proc, but does have embedded FPA -# (the FPA part is no-longer supported). -begin cpu arm7500fe - tune flags CO_PROC WBUF - architecture armv3 - costs slowmul -end cpu arm7500fe - - -# V3M Architecture Processors -# arm7m doesn't exist on its own, but only with "D", (and "I"), but -# those don't alter the code, so arm7m is sometimes used. -begin cpu arm7m - tune flags CO_PROC - architecture armv3m - costs fastmul -end cpu arm7m - -begin cpu arm7dm - tune flags CO_PROC - architecture armv3m - costs fastmul -end cpu arm7dm - -begin cpu arm7dmi - tune flags CO_PROC - architecture armv3m - costs fastmul -end cpu arm7dmi - - # V4 Architecture Processors begin cpu arm8 tune flags LDSCHED diff --git a/gcc/config/arm/arm-fixed.md b/gcc/config/arm/arm-fixed.md index b1451e038957c1eb8c8717c25ba079284c3f7c65..18a564bffd78c884e436e2d6de7c19c2fecb5e47 100644 --- a/gcc/config/arm/arm-fixed.md +++ b/gcc/config/arm/arm-fixed.md @@ -137,7 +137,7 @@ (define_expand "mulsq3" [(set (match_operand:SQ 0 "s_register_operand" "") (mult:SQ (match_operand:SQ 1 "s_register_operand" "") (match_operand:SQ 2 "s_register_operand" "")))] - "TARGET_32BIT && arm_arch3m" + "TARGET_32BIT" { rtx tmp1 = gen_reg_rtx (DImode); rtx tmp2 = gen_reg_rtx (SImode); @@ -159,7 +159,7 @@ (define_expand "mulsa3" [(set (match_operand:SA 0 "s_register_operand" "") (mult:SA (match_operand:SA 1 "s_register_operand" "") (match_operand:SA 2 "s_register_operand" "")))] - "TARGET_32BIT && arm_arch3m" + "TARGET_32BIT" { rtx tmp1 = gen_reg_rtx (DImode); rtx tmp2 = gen_reg_rtx (SImode); @@ -178,7 +178,7 @@ (define_expand "mulusa3" [(set (match_operand:USA 0 "s_register_operand" "") (mult:USA (match_operand:USA 1 "s_register_operand" "") (match_operand:USA 2 "s_register_operand" "")))] - "TARGET_32BIT && arm_arch3m" + "TARGET_32BIT" { rtx tmp1 = gen_reg_rtx (DImode); rtx tmp2 = gen_reg_rtx (SImode); diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index ea2cf694f2fc6a7337accb0a7f7044fc99a7630d..8537262ce644bbacd7a800c708bcd86eea93d2bd 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -379,9 +379,6 @@ extern bool arm_is_constant_pool_ref (rtx); be used. */ extern unsigned int tune_flags; -/* Nonzero if this chip supports the ARM Architecture 3M extensions. */ -extern int arm_arch3m; - /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ extern int arm_arch4; diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index b05da649ac580655142cb8f27adf8717d135b911..0ffb4c86ca46718bbfaf65eb41ab8e87f924e903 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -25,75 +25,6 @@ Name(processor_type) Type(enum processor_type) Known ARM CPUs (for use with the -mcpu= and -mtune= options): EnumValue -Enum(processor_type) String(arm2) Value( TARGET_CPU_arm2) - -EnumValue -Enum(processor_type) String(arm250) Value( TARGET_CPU_arm250) - -EnumValue -Enum(processor_type) String(arm3) Value( TARGET_CPU_arm3) - -EnumValue -Enum(processor_type) String(arm6) Value( TARGET_CPU_arm6) - -EnumValue -Enum(processor_type) String(arm60) Value( TARGET_CPU_arm60) - -EnumValue -Enum(processor_type) String(arm600) Value( TARGET_CPU_arm600) - -EnumValue -Enum(processor_type) String(arm610) Value( TARGET_CPU_arm610) - -EnumValue -Enum(processor_type) String(arm620) Value( TARGET_CPU_arm620) - -EnumValue -Enum(processor_type) String(arm7) Value( TARGET_CPU_arm7) - -EnumValue -Enum(processor_type) String(arm7d) Value( TARGET_CPU_arm7d) - -EnumValue -Enum(processor_type) String(arm7di) Value( TARGET_CPU_arm7di) - -EnumValue -Enum(processor_type) String(arm70) Value( TARGET_CPU_arm70) - -EnumValue -Enum(processor_type) String(arm700) Value( TARGET_CPU_arm700) - -EnumValue -Enum(processor_type) String(arm700i) Value( TARGET_CPU_arm700i) - -EnumValue -Enum(processor_type) String(arm710) Value( TARGET_CPU_arm710) - -EnumValue -Enum(processor_type) String(arm720) Value( TARGET_CPU_arm720) - -EnumValue -Enum(processor_type) String(arm710c) Value( TARGET_CPU_arm710c) - -EnumValue -Enum(processor_type) String(arm7100) Value( TARGET_CPU_arm7100) - -EnumValue -Enum(processor_type) String(arm7500) Value( TARGET_CPU_arm7500) - -EnumValue -Enum(processor_type) String(arm7500fe) Value( TARGET_CPU_arm7500fe) - -EnumValue -Enum(processor_type) String(arm7m) Value( TARGET_CPU_arm7m) - -EnumValue -Enum(processor_type) String(arm7dm) Value( TARGET_CPU_arm7dm) - -EnumValue -Enum(processor_type) String(arm7dmi) Value( TARGET_CPU_arm7dmi) - -EnumValue Enum(processor_type) String(arm8) Value( TARGET_CPU_arm8) EnumValue @@ -365,106 +296,94 @@ Name(arm_arch) Type(int) Known ARM architectures (for use with the -march= option): EnumValue -Enum(arm_arch) String(armv2) Value(0) - -EnumValue -Enum(arm_arch) String(armv2a) Value(1) - -EnumValue -Enum(arm_arch) String(armv3) Value(2) - -EnumValue -Enum(arm_arch) String(armv3m) Value(3) - -EnumValue -Enum(arm_arch) String(armv4) Value(4) +Enum(arm_arch) String(armv4) Value(0) EnumValue -Enum(arm_arch) String(armv4t) Value(5) +Enum(arm_arch) String(armv4t) Value(1) EnumValue -Enum(arm_arch) String(armv5t) Value(6) +Enum(arm_arch) String(armv5t) Value(2) EnumValue -Enum(arm_arch) String(armv5te) Value(7) +Enum(arm_arch) String(armv5te) Value(3) EnumValue -Enum(arm_arch) String(armv5tej) Value(8) +Enum(arm_arch) String(armv5tej) Value(4) EnumValue -Enum(arm_arch) String(armv6) Value(9) +Enum(arm_arch) String(armv6) Value(5) EnumValue -Enum(arm_arch) String(armv6j) Value(10) +Enum(arm_arch) String(armv6j) Value(6) EnumValue -Enum(arm_arch) String(armv6k) Value(11) +Enum(arm_arch) String(armv6k) Value(7) EnumValue -Enum(arm_arch) String(armv6z) Value(12) +Enum(arm_arch) String(armv6z) Value(8) EnumValue -Enum(arm_arch) String(armv6kz) Value(13) +Enum(arm_arch) String(armv6kz) Value(9) EnumValue -Enum(arm_arch) String(armv6zk) Value(14) +Enum(arm_arch) String(armv6zk) Value(10) EnumValue -Enum(arm_arch) String(armv6t2) Value(15) +Enum(arm_arch) String(armv6t2) Value(11) EnumValue -Enum(arm_arch) String(armv6-m) Value(16) +Enum(arm_arch) String(armv6-m) Value(12) EnumValue -Enum(arm_arch) String(armv6s-m) Value(17) +Enum(arm_arch) String(armv6s-m) Value(13) EnumValue -Enum(arm_arch) String(armv7) Value(18) +Enum(arm_arch) String(armv7) Value(14) EnumValue -Enum(arm_arch) String(armv7-a) Value(19) +Enum(arm_arch) String(armv7-a) Value(15) EnumValue -Enum(arm_arch) String(armv7ve) Value(20) +Enum(arm_arch) String(armv7ve) Value(16) EnumValue -Enum(arm_arch) String(armv7-r) Value(21) +Enum(arm_arch) String(armv7-r) Value(17) EnumValue -Enum(arm_arch) String(armv7-m) Value(22) +Enum(arm_arch) String(armv7-m) Value(18) EnumValue -Enum(arm_arch) String(armv7e-m) Value(23) +Enum(arm_arch) String(armv7e-m) Value(19) EnumValue -Enum(arm_arch) String(armv8-a) Value(24) +Enum(arm_arch) String(armv8-a) Value(20) EnumValue -Enum(arm_arch) String(armv8.1-a) Value(25) +Enum(arm_arch) String(armv8.1-a) Value(21) EnumValue -Enum(arm_arch) String(armv8.2-a) Value(26) +Enum(arm_arch) String(armv8.2-a) Value(22) EnumValue -Enum(arm_arch) String(armv8.3-a) Value(27) +Enum(arm_arch) String(armv8.3-a) Value(23) EnumValue -Enum(arm_arch) String(armv8.4-a) Value(28) +Enum(arm_arch) String(armv8.4-a) Value(24) EnumValue -Enum(arm_arch) String(armv8-m.base) Value(29) +Enum(arm_arch) String(armv8-m.base) Value(25) EnumValue -Enum(arm_arch) String(armv8-m.main) Value(30) +Enum(arm_arch) String(armv8-m.main) Value(26) EnumValue -Enum(arm_arch) String(armv8-r) Value(31) +Enum(arm_arch) String(armv8-r) Value(27) EnumValue -Enum(arm_arch) String(iwmmxt) Value(32) +Enum(arm_arch) String(iwmmxt) Value(28) EnumValue -Enum(arm_arch) String(iwmmxt2) Value(33) +Enum(arm_arch) String(iwmmxt2) Value(29) Enum Name(arm_fpu) Type(enum fpu_type) diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index df43a1ccbb24fc2dd427ebac9b1186b72d3b016f..877e3465147b8b829166b8c0f9c464ca38e0b73a 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -21,42 +21,34 @@ ; . (define_attr "tune" - "arm2,arm250,arm3, - arm6,arm60,arm600, - arm610,arm620,arm7, - arm7d,arm7di,arm70, - arm700,arm700i,arm710, - arm720,arm710c,arm7100, - arm7500,arm7500fe,arm7m, - arm7dm,arm7dmi,arm8, - arm810,strongarm,strongarm110, - strongarm1100,strongarm1110,fa526, - fa626,arm7tdmi,arm7tdmis, - arm710t,arm720t,arm740t, - arm9,arm9tdmi,arm920, - arm920t,arm922t,arm940t, - ep9312,arm10tdmi,arm1020t, - arm9e,arm946es,arm966es, - arm968es,arm10e,arm1020e, - arm1022e,xscale,iwmmxt, - iwmmxt2,fa606te,fa626te, - fmp626,fa726te,arm926ejs, - arm1026ejs,arm1136js,arm1136jfs, - arm1176jzs,arm1176jzfs,mpcorenovfp, - mpcore,arm1156t2s,arm1156t2fs, - cortexm1,cortexm0,cortexm0plus, - cortexm1smallmultiply,cortexm0smallmultiply,cortexm0plussmallmultiply, - genericv7a,cortexa5,cortexa7, - cortexa8,cortexa9,cortexa12, - cortexa15,cortexa17,cortexr4, - cortexr4f,cortexr5,cortexr7, - cortexr8,cortexm7,cortexm4, - cortexm3,marvell_pj4,cortexa15cortexa7, - cortexa17cortexa7,cortexa32,cortexa35, - cortexa53,cortexa57,cortexa72, - cortexa73,exynosm1,xgene1, - cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35, - cortexa73cortexa53,cortexa55,cortexa75, - cortexa75cortexa55,cortexm23,cortexm33, - cortexr52" + "arm8,arm810,strongarm, + strongarm110,strongarm1100,strongarm1110, + fa526,fa626,arm7tdmi, + arm7tdmis,arm710t,arm720t, + arm740t,arm9,arm9tdmi, + arm920,arm920t,arm922t, + arm940t,ep9312,arm10tdmi, + arm1020t,arm9e,arm946es, + arm966es,arm968es,arm10e, + arm1020e,arm1022e,xscale, + iwmmxt,iwmmxt2,fa606te, + fa626te,fmp626,fa726te, + arm926ejs,arm1026ejs,arm1136js, + arm1136jfs,arm1176jzs,arm1176jzfs, + mpcorenovfp,mpcore,arm1156t2s, + arm1156t2fs,cortexm1,cortexm0, + cortexm0plus,cortexm1smallmultiply,cortexm0smallmultiply, + cortexm0plussmallmultiply,genericv7a,cortexa5, + cortexa7,cortexa8,cortexa9, + cortexa12,cortexa15,cortexa17, + cortexr4,cortexr4f,cortexr5, + cortexr7,cortexr8,cortexm7, + cortexm4,cortexm3,marvell_pj4, + cortexa15cortexa7,cortexa17cortexa7,cortexa32, + cortexa35,cortexa53,cortexa57, + cortexa72,cortexa73,exynosm1, + xgene1,cortexa57cortexa53,cortexa72cortexa53, + cortexa73cortexa35,cortexa73cortexa53,cortexa55, + cortexa75,cortexa75cortexa55,cortexm23, + cortexm33,cortexr52" (const (symbol_ref "((enum attr_tune) arm_tune)"))) diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index f3a6f7db95ef4806ea0677babe503cd9d62d40a3..34894c090dd6eafeeddbb260f0b5ad2c29003581 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -399,9 +399,6 @@ enum base_architecture /* The major revision number of the ARM Architecture implemented by the target. */ extern enum base_architecture arm_base_arch; -/* Nonzero if this chip supports the ARM Architecture 3M extensions. */ -extern int arm_arch3m; - /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ extern int arm_arch4; diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 3bfc0d5ec0e8e455a169d595d1f1c926c4ac349b..4a5da7e45a7698bc052d423bef7ed8a4404164db 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -850,9 +850,6 @@ struct arm_build_target arm_active_target; /* The following are used in the arm.md file as equivalents to bits in the above two flag variables. */ -/* Nonzero if this chip supports the ARM Architecture 3M extensions. */ -int arm_arch3m = 0; - /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ int arm_arch4 = 0; @@ -3002,7 +2999,8 @@ arm_option_override_internal (struct gcc_options *opts, if (TARGET_INTERWORK && !bitmap_bit_p (arm_active_target.isa, isa_bit_thumb)) { /* The default is to enable interworking, so this warning message would - be confusing to users who have just compiled with, eg, -march=armv3. */ + be confusing to users who have just compiled with + eg, -march=armv4. */ /* warning (0, "ignoring -minterwork because target CPU does not support THUMB"); */ opts->x_target_flags &= ~MASK_INTERWORK; } @@ -3236,7 +3234,6 @@ arm_configure_build_target (struct arm_build_target *target, if (TARGET_INTERWORK || TARGET_THUMB) { bitmap_set_bit (sought_isa, isa_bit_thumb); - bitmap_set_bit (sought_isa, isa_bit_mode32); /* There are no ARM processors that support both APCS-26 and interworking. Therefore we forcibly remove MODE26 from @@ -3636,7 +3633,6 @@ arm_option_reconfigure_globals (void) /* Initialize boolean versions of the architectural flags, for use in the arm.md file. */ - arm_arch3m = bitmap_bit_p (arm_active_target.isa, isa_bit_armv3m); arm_arch4 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv4); arm_arch4t = arm_arch4 && bitmap_bit_p (arm_active_target.isa, isa_bit_thumb); arm_arch5t = bitmap_bit_p (arm_active_target.isa, isa_bit_armv5t); @@ -10005,8 +10001,7 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code, if (mode == DImode) { - if (arm_arch3m - && GET_CODE (XEXP (x, 0)) == MULT + if (GET_CODE (XEXP (x, 0)) == MULT && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND && GET_CODE (XEXP (XEXP (x, 0), 1)) == ZERO_EXTEND) || (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND @@ -10204,11 +10199,10 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code, if (mode == DImode) { - if (arm_arch3m - && ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND - && GET_CODE (XEXP (x, 1)) == ZERO_EXTEND) - || (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND - && GET_CODE (XEXP (x, 1)) == SIGN_EXTEND))) + if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND + && GET_CODE (XEXP (x, 1)) == ZERO_EXTEND) + || (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND + && GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)) { if (speed_p) *cost += extra_cost->mult[1].extend; diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 118cecfffdd9f312fb6371797d4d7d28cc877ba1..361a02668b0cfc9780c68a1eaf4a56fdf69b3d9d 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1754,7 +1754,7 @@ (define_expand "maddsidi4" (sign_extend:DI (match_operand:SI 1 "s_register_operand" "")) (sign_extend:DI (match_operand:SI 2 "s_register_operand" ""))) (match_operand:DI 3 "s_register_operand" "")))] - "TARGET_32BIT && arm_arch3m" + "TARGET_32BIT" "") (define_insn "*mulsidi3adddi" @@ -1764,7 +1764,7 @@ (define_insn "*mulsidi3adddi" (sign_extend:DI (match_operand:SI 2 "s_register_operand" "%r")) (sign_extend:DI (match_operand:SI 3 "s_register_operand" "r"))) (match_operand:DI 1 "s_register_operand" "0")))] - "TARGET_32BIT && arm_arch3m && !arm_arch6" + "TARGET_32BIT && !arm_arch6" "smlal%?\\t%Q0, %R0, %3, %2" [(set_attr "type" "smlal") (set_attr "predicable" "yes")] @@ -1794,7 +1794,7 @@ (define_expand "mulsidi3" (mult:DI (sign_extend:DI (match_operand:SI 1 "s_register_operand" "")) (sign_extend:DI (match_operand:SI 2 "s_register_operand" ""))))] - "TARGET_32BIT && arm_arch3m" + "TARGET_32BIT" "" ) @@ -1803,7 +1803,7 @@ (define_insn "*mulsidi3_nov6" (mult:DI (sign_extend:DI (match_operand:SI 1 "s_register_operand" "%r")) (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))] - "TARGET_32BIT && arm_arch3m && !arm_arch6" + "TARGET_32BIT && !arm_arch6" "smull%?\\t%Q0, %R0, %1, %2" [(set_attr "type" "smull") (set_attr "predicable" "yes")] @@ -1825,7 +1825,7 @@ (define_expand "umulsidi3" (mult:DI (zero_extend:DI (match_operand:SI 1 "s_register_operand" "")) (zero_extend:DI (match_operand:SI 2 "s_register_operand" ""))))] - "TARGET_32BIT && arm_arch3m" + "TARGET_32BIT" "" ) @@ -1834,7 +1834,7 @@ (define_insn "*umulsidi3_nov6" (mult:DI (zero_extend:DI (match_operand:SI 1 "s_register_operand" "%r")) (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))] - "TARGET_32BIT && arm_arch3m && !arm_arch6" + "TARGET_32BIT && !arm_arch6" "umull%?\\t%Q0, %R0, %1, %2" [(set_attr "type" "umull") (set_attr "predicable" "yes")] @@ -1858,7 +1858,7 @@ (define_expand "umaddsidi4" (zero_extend:DI (match_operand:SI 1 "s_register_operand" "")) (zero_extend:DI (match_operand:SI 2 "s_register_operand" ""))) (match_operand:DI 3 "s_register_operand" "")))] - "TARGET_32BIT && arm_arch3m" + "TARGET_32BIT" "") (define_insn "*umulsidi3adddi" @@ -1868,7 +1868,7 @@ (define_insn "*umulsidi3adddi" (zero_extend:DI (match_operand:SI 2 "s_register_operand" "%r")) (zero_extend:DI (match_operand:SI 3 "s_register_operand" "r"))) (match_operand:DI 1 "s_register_operand" "0")))] - "TARGET_32BIT && arm_arch3m && !arm_arch6" + "TARGET_32BIT && !arm_arch6" "umlal%?\\t%Q0, %R0, %3, %2" [(set_attr "type" "umlal") (set_attr "predicable" "yes")] @@ -1897,7 +1897,7 @@ (define_expand "smulsi3_highpart" (sign_extend:DI (match_operand:SI 2 "s_register_operand" ""))) (const_int 32)))) (clobber (match_scratch:SI 3 ""))])] - "TARGET_32BIT && arm_arch3m" + "TARGET_32BIT" "" ) @@ -1910,7 +1910,7 @@ (define_insn "*smulsi3_highpart_nov6" (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r"))) (const_int 32)))) (clobber (match_scratch:SI 3 "=&r,&r"))] - "TARGET_32BIT && arm_arch3m && !arm_arch6" + "TARGET_32BIT && !arm_arch6" "smull%?\\t%3, %0, %2, %1" [(set_attr "type" "smull") (set_attr "predicable" "yes")] @@ -1941,7 +1941,7 @@ (define_expand "umulsi3_highpart" (zero_extend:DI (match_operand:SI 2 "s_register_operand" ""))) (const_int 32)))) (clobber (match_scratch:SI 3 ""))])] - "TARGET_32BIT && arm_arch3m" + "TARGET_32BIT" "" ) @@ -1954,7 +1954,7 @@ (define_insn "*umulsi3_highpart_nov6" (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r"))) (const_int 32)))) (clobber (match_scratch:SI 3 "=&r,&r"))] - "TARGET_32BIT && arm_arch3m && !arm_arch6" + "TARGET_32BIT && !arm_arch6" "umull%?\\t%3, %0, %2, %1" [(set_attr "type" "umull") (set_attr "predicable" "yes")] diff --git a/gcc/config/arm/t-arm-elf b/gcc/config/arm/t-arm-elf index aa36ff08d783a1c7281d4d9e14c1243cc263e4d4..3506b16e929fa30af90e0a1bf20653ed6a098eaa 100644 --- a/gcc/config/arm/t-arm-elf +++ b/gcc/config/arm/t-arm-elf @@ -39,7 +39,7 @@ v7ve_fps := vfpv3-d16 vfpv3 vfpv3-d16-fp16 vfpv3-fp16 vfpv4 neon \ v8_fps := simd fp16 crypto fp16+crypto dotprod fp16fml # We don't do anything special with these. Pre-v4t probably doesn't work. -all_early_nofp := armv2 armv2a armv3 armv3m armv4 armv4t armv5t +all_early_nofp := armv4 armv4t armv5t all_early_arch := armv5tej armv6 armv6j armv6k armv6z armv6kz \ armv6zk armv6t2 iwmmxt iwmmxt2 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 8ed8fbbeab49deb570e8ad30eee024f8ba1e5ed8..47ce28081dc0a3d3f45a7d4c5728cf5abfb3d147 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -15900,9 +15900,7 @@ Permissible names are: @samp{iwmmxt} and @samp{iwmmxt2}. Additionally, the following architectures, which lack support for the -Thumb execution state, are recognized but support is deprecated: -@samp{armv2}, @samp{armv2a}, @samp{armv3}, @samp{armv3m}, -@samp{armv4}. +Thumb execution state, are recognized but support is deprecated: @samp{armv4}. Many of the architectures support extensions. These can be added by appending @samp{+@var{extension}} to the architecture name. Extension diff --git a/gcc/testsuite/gcc.target/arm/pr62554.c b/gcc/testsuite/gcc.target/arm/pr62554.c deleted file mode 100644 index 4d6501cba1fb5122cfa9e276766280414c338225..0000000000000000000000000000000000000000 --- a/gcc/testsuite/gcc.target/arm/pr62554.c +++ /dev/null @@ -1,51 +0,0 @@ -/* Check that pre ARMv4 compilation still works. */ -/* { dg-do compile } */ -/* { dg-options "-marm -march=armv3 -O" } */ -/* { dg-require-effective-target arm_arm_ok } */ - -typedef struct -{ - char bits; - short val; -} code; - -union uu -{ - short us; - char b[2]; -}; - -int a, b, c, f, g, h; -code *d; - -code e; - -int -fn1 (void) -{ - char i; - do - if (e.bits) - { - dodist: - f = c; - if (e.bits & 6) - { - ++i; - if (g) - do - { - union uu j; - j.b[1] = a; - h = j.us; - } - while (fn1); - } - else - { - e = d[b]; - goto dodist; - } - } - while (i); -} diff --git a/gcc/testsuite/gcc.target/arm/pr69610-1.c b/gcc/testsuite/gcc.target/arm/pr69610-1.c deleted file mode 100644 index a671b93392bdac8679415cb49a3691dcbe672790..0000000000000000000000000000000000000000 --- a/gcc/testsuite/gcc.target/arm/pr69610-1.c +++ /dev/null @@ -1,14 +0,0 @@ -/* Check that pre ARMv4 compilation still works. */ -/* { dg-do compile } */ -/* { dg-options "-marm -march=armv3 -ftree-ter" } */ -/* { dg-require-effective-target arm_arm_ok } */ - -typedef unsigned short v16u16 __attribute__ ((vector_size (16))); -typedef unsigned int v16u32 __attribute__ ((vector_size (16))); - -unsigned short -foo (v16u16 v16u16_1, v16u32 v16u32_1) -{ - v16u16_1 += (v16u16) v16u32_1; - return v16u16_1[5] + v16u32_1[1]; -} diff --git a/gcc/testsuite/gcc.target/arm/pr69610-2.c b/gcc/testsuite/gcc.target/arm/pr69610-2.c deleted file mode 100644 index e932c63b63962d95eff02ba26430e7eef454329f..0000000000000000000000000000000000000000 --- a/gcc/testsuite/gcc.target/arm/pr69610-2.c +++ /dev/null @@ -1,33 +0,0 @@ -/* Check that pre ARMv4 compilation still works. */ -/* { dg-do compile } */ -/* { dg-options "-marm -march=armv3 -O2 -fno-forward-propagate" } */ -/* { dg-require-effective-target arm_arm_ok } */ - -typedef short v16u16 __attribute__ ((vector_size (16))); -typedef unsigned v16u32 __attribute__ ((vector_size (16))); -typedef long long v16u64 __attribute__ ((vector_size (16))); - -unsigned -foo - (int - u16_0, - unsigned - u32_0, - int - u64_0, - int - u16_1, - unsigned - u64_1, - v16u16 - v16u16_0, - v16u32 - v16u32_0, - v16u64 v16u64_0, v16u16 v16u16_1, v16u32 v16u32_1, v16u64 v16u64_1) -{ - v16u16_1[3] -= v16u32_0[0]; - v16u16_0 -= (v16u16) v16u32_0; - return u16_0 + u32_0 + u64_0 + u16_1 + - v16u16_0[0] + v16u16_0[2] + v16u16_0[3] + v16u16_0[4] + v16u16_0[5] + v16u32_0[0] + v16u32_0[1] + v16u32_0[3] + v16u64_0[1] + - v16u16_1[2] + v16u16_1[3] + v16u16_1[5] + v16u16_1[7] + v16u32_1[0] + v16u32_1[3] + v16u64_1[0] + v16u64_1[1]; -}