From patchwork Wed May 16 22:29:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 914993 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="WCkNwAl+"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40mV2w0djZz9s0q for ; Thu, 17 May 2018 08:48:24 +1000 (AEST) Received: from localhost ([::1]:44880 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ5DZ-0004Pj-Iv for incoming@patchwork.ozlabs.org; Wed, 16 May 2018 18:48:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41220) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4wL-0007kO-TL for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4wK-0007Wk-Sa for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:33 -0400 Received: from mail-pl0-x241.google.com ([2607:f8b0:400e:c01::241]:40157) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4wK-0007W7-HN for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:32 -0400 Received: by mail-pl0-x241.google.com with SMTP id t12-v6so1244645plo.7 for ; Wed, 16 May 2018 15:30:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aEw+icNHDVvyjfO6zFShh6ZmP/DNMAOE4EL6agkNtMo=; b=WCkNwAl+4oo1DRZ7cbZ+3ss+BBw1DSNNjctGX9npqcFZKhN3Z+e/9+4cFyfV1TOmBv DH4m1HGFbtjLjKeCdROGe/R4QsjFShf/WK03VTzhqnrZovOjWXJ7VBYdXsAEqv1H1lvS ITc2evKEnlk8bG9Lhw0uxKmAAgtsCY0+fR1Is= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aEw+icNHDVvyjfO6zFShh6ZmP/DNMAOE4EL6agkNtMo=; b=tjOCyHIchm7DVEj6/SvsLHfk2tZsRgWhTUZukZqFniURCk8ryufaYSJKnQEkrL9rrC D6fEetE9AvPU/xcl8O/RwfhsSibgF9vHVkDTOGO4mkIxfysJJRcCyOxzqbcEljp+O0w+ F1qG+CWuQd3arenJ/aIF7z1Iub5QvcZVRIt7g5k0y262ohBowKaxnl19iaRlGiCc3dJZ BxzbzgfSRJXKBPuZyFL1lxOq/o9Rde4jGjkOwd+DaD63EEk9J51ka2tbhaOeKWbQkocP xU2Ml2M+zAeRt1W9moIMZu++jQ1W16G83Tn4OJe/zuckR8EkxpBbq9+TnO2CYuY8WqTg J4UQ== X-Gm-Message-State: ALKqPwe1+0s3S7l02y3m9KApj92IS30dy92mJp7+D+rPkqq7qbxH+D/D KCJeCe0li7gyxteCxcP4VUyPVw/PTKc= X-Google-Smtp-Source: AB8JxZrU+/zhcbo+f6RDwpY5sR/jDTASjYE6tTSjZ4Yinwu3v+9/0m9qWZRPPRdigXw4JDbArRaxuA== X-Received: by 2002:a17:902:710f:: with SMTP id a15-v6mr2758561pll.171.1526509831287; Wed, 16 May 2018 15:30:31 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:29:55 -0700 Message-Id: <20180516223007.10256-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v3-a 15/27] target/arm: Implement SVE Integer Arithmetic - Unpredicated Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 34 ++++++++++++++++++++++++++++++++++ target/arm/sve.decode | 13 +++++++++++++ 2 files changed, 47 insertions(+) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index f14bb2196a..d9c4118d46 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -251,6 +251,40 @@ static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm); } +/* + *** SVE Integer Arithmetic - Unpredicated Group + */ + +static bool trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + return do_vector3_z(s, tcg_gen_gvec_add, a->esz, a->rd, a->rn, a->rm); +} + +static bool trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + return do_vector3_z(s, tcg_gen_gvec_sub, a->esz, a->rd, a->rn, a->rm); +} + +static bool trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + return do_vector3_z(s, tcg_gen_gvec_ssadd, a->esz, a->rd, a->rn, a->rm); +} + +static bool trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + return do_vector3_z(s, tcg_gen_gvec_sssub, a->esz, a->rd, a->rn, a->rm); +} + +static bool trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + return do_vector3_z(s, tcg_gen_gvec_usadd, a->esz, a->rd, a->rn, a->rm); +} + +static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + return do_vector3_z(s, tcg_gen_gvec_ussub, a->esz, a->rd, a->rn, a->rm); +} + /* *** SVE Integer Arithmetic - Binary Predicated Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 5e4335b2ae..58d59c7b77 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -66,6 +66,9 @@ # Three predicate operand, with governing predicate, flag setting @pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s +# Three operand, vector element size +@rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz + # Two register operand, with governing predicate, vector element size @rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \ &rprr_esz rn=%reg_movprfx @@ -203,6 +206,16 @@ MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB +### SVE Integer Arithmetic - Unpredicated Group + +# SVE integer add/subtract vectors (unpredicated) +ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm +SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm +SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm +UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm +SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm +UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm + ### SVE Logical - Unpredicated Group # SVE bitwise logical operations (unpredicated)