From patchwork Wed May 16 22:29:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 914975 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="EHdeLlsd"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40mTl36D6Gz9s19 for ; Thu, 17 May 2018 08:34:39 +1000 (AEST) Received: from localhost ([::1]:44766 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ50H-0001ir-DY for incoming@patchwork.ozlabs.org; Wed, 16 May 2018 18:34:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40930) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4w5-0007Rm-1w for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4w3-0007Ka-QJ for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:17 -0400 Received: from mail-pl0-x229.google.com ([2607:f8b0:400e:c01::229]:43851) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4w3-0007Jr-JS for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:15 -0400 Received: by mail-pl0-x229.google.com with SMTP id c41-v6so1239758plj.10 for ; Wed, 16 May 2018 15:30:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6FkDAGxpjtctRPD74Kvsj7pbO4IsIUxfkCQDo+Nmo7Q=; b=EHdeLlsd8AY3TQ0HLEU47faoNa6YDQzmrrI8zSz3SRNbbpz7Zdd5F4Y4qG7jTsvDFf llJ4sdtdZw0/KHKl1Ij6/l6+ZdHixWOfhKha4gbQDV/fCIdFCmhnwy8cx7JsasgEgqXU JBzTzIADCwHnpUnmmArQ83wd4aq17CYSmbMlI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6FkDAGxpjtctRPD74Kvsj7pbO4IsIUxfkCQDo+Nmo7Q=; b=ndxA1PgIdQwuFZ3Jgp0HBz/TGVQWy4NNH8NZYI/Tc6ItCufb8qlgQ6Rux1h2QWzpy7 8t7n7L25bXG5WdlzkM8rYqOIhHWjMFJU5C32EkfVWA7LIgjlAGCs/KUATGBl8F4nIqt3 B1mcKN5i44q0iLlIzxA8o/RLUffDwiP5cGdGZMjmN4FC2XKjBarmvvCKbmYUhKI2E6R9 c05+8BlfUQYe8QpCKLbyqeLcBJKCjr4QXjHpLhTpZ7ztP5DeLzUom2wwgpMdG5yfjTg+ 5pFVKrmD5impb4imF5/mWyPWyPqBEvrryWOc4ZPNZshmfkSdMmkPqOnc4N7OzgvdqbcU KRQw== X-Gm-Message-State: ALKqPwdLYViDAKpfNHr4g74kTQYDWUd4zlmgQbr1xujRc2XXjb9SxLzU vo9hNz8IUf63nOJ4jlCa1OKJzvOjd0Q= X-Google-Smtp-Source: AB8JxZq+WPKwT4huwBiyXGEKtVuwX3LJTQxyjlJjKoNfFuVqFjbfQmha3RDZCmSLgtXS4Zdi81/p7A== X-Received: by 2002:a17:902:22a:: with SMTP id 39-v6mr2715823plc.146.1526509814365; Wed, 16 May 2018 15:30:14 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:29:43 -0700 Message-Id: <20180516223007.10256-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::229 Subject: [Qemu-devel] [PATCH v3-a 03/27] target/arm: Implement SVE Bitwise Logical - Unpredicated Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" These were the instructions that were stubbed out when introducing the decode skeleton. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Remove typedefs now present in translate-a64.h. --- target/arm/translate-sve.c | 55 ++++++++++++++++++++++++++++++++------ 1 file changed, 47 insertions(+), 8 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index d323bd0b67..67d6db313e 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -42,22 +42,61 @@ * Implement all of the translator functions referenced by the decoder. */ -static bool trans_AND_zzz(DisasContext *s, arg_AND_zzz *a, uint32_t insn) +/* Invoke a vector expander on two Zregs. */ +static bool do_vector2_z(DisasContext *s, GVecGen2Fn *gvec_fn, + int esz, int rd, int rn) { - return false; + if (sve_access_check(s)) { + unsigned vsz = vec_full_reg_size(s); + gvec_fn(esz, vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), vsz, vsz); + } + return true; } -static bool trans_ORR_zzz(DisasContext *s, arg_ORR_zzz *a, uint32_t insn) +/* Invoke a vector expander on three Zregs. */ +static bool do_vector3_z(DisasContext *s, GVecGen3Fn *gvec_fn, + int esz, int rd, int rn, int rm) { - return false; + if (sve_access_check(s)) { + unsigned vsz = vec_full_reg_size(s); + gvec_fn(esz, vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), vsz, vsz); + } + return true; } -static bool trans_EOR_zzz(DisasContext *s, arg_EOR_zzz *a, uint32_t insn) +/* Invoke a vector move on two Zregs. */ +static bool do_mov_z(DisasContext *s, int rd, int rn) { - return false; + return do_vector2_z(s, tcg_gen_gvec_mov, 0, rd, rn); } -static bool trans_BIC_zzz(DisasContext *s, arg_BIC_zzz *a, uint32_t insn) +/* + *** SVE Logical - Unpredicated Group + */ + +static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) { - return false; + return do_vector3_z(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->rm); +} + +static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + if (a->rn == a->rm) { /* MOV */ + return do_mov_z(s, a->rd, a->rn); + } else { + return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm); + } +} + +static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + return do_vector3_z(s, tcg_gen_gvec_xor, 0, a->rd, a->rn, a->rm); +} + +static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm); }