From patchwork Wed May 16 17:43:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rishabh Bhatnagar X-Patchwork-Id: 914834 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=codeaurora.org header.i=@codeaurora.org header.b="CjkKInP+"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="CjkKInP+"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40mMJj6JXYz9s2L for ; Thu, 17 May 2018 03:44:53 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751227AbeEPRn5 (ORCPT ); Wed, 16 May 2018 13:43:57 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:36186 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751130AbeEPRn4 (ORCPT ); Wed, 16 May 2018 13:43:56 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 7904560A00; Wed, 16 May 2018 17:43:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1526492635; bh=Nflz/VQYbVowpGISYc0Yt1SlTvz7NVyEygeqWFY+Fww=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CjkKInP+bRd0q+IGGsOrajl4EArL7qUjh2tC7ZHd5xnxTBlVQ5two2P1GgHOLSBEs Xl/+297UtP7UffO0qg3nhr3xnEFyQ7tCd7PwkhJlznOa7R6Q4y4bdkb0hqAEZ5WGKD 57AWaWV6S4Ik1EThfPXAxFM+g2lMF5BHS/tggVc0= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED, T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from rishabhb-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: rishabhb@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 9751660A00; Wed, 16 May 2018 17:43:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1526492635; bh=Nflz/VQYbVowpGISYc0Yt1SlTvz7NVyEygeqWFY+Fww=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CjkKInP+bRd0q+IGGsOrajl4EArL7qUjh2tC7ZHd5xnxTBlVQ5two2P1GgHOLSBEs Xl/+297UtP7UffO0qg3nhr3xnEFyQ7tCd7PwkhJlznOa7R6Q4y4bdkb0hqAEZ5WGKD 57AWaWV6S4Ik1EThfPXAxFM+g2lMF5BHS/tggVc0= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 9751660A00 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=rishabhb@codeaurora.org From: Rishabh Bhatnagar To: linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm@lists.infradead.org, tsoni@codeaurora.org, ckadabi@codeaurora.org, evgreen@chromium.org, robh@kernel.org, Rishabh Bhatnagar Subject: [PATCH v7 1/2] dt-bindings: Documentation for qcom, llcc Date: Wed, 16 May 2018 10:43:42 -0700 Message-Id: <1526492623-20527-2-git-send-email-rishabhb@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1526492623-20527-1-git-send-email-rishabhb@codeaurora.org> References: <1526492623-20527-1-git-send-email-rishabhb@codeaurora.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Documentation for last level cache controller device tree bindings, client bindings usage examples. Signed-off-by: Channagoud Kadabi Signed-off-by: Rishabh Bhatnagar Reviewed-by: Rob Herring --- .../devicetree/bindings/arm/msm/qcom,llcc.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt new file mode 100644 index 0000000..0ebbf0a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt @@ -0,0 +1,26 @@ +== Introduction== + +LLCC (Last Level Cache Controller) provides last level of cache memory in SOC, +that can be shared by multiple clients. Clients here are different cores in the +SOC, the idea is to minimize the local caches at the clients and migrate to +common pool of memory. Cache memory is divided into partitions called slices +which are assigned to clients. Clients can query the slice details, activate +and deactivate them. + +Properties: +- compatible: + Usage: required + Value type: + Definition: must be "qcom,sdm845-llcc" + +- reg: + Usage: required + Value Type: + Definition: Start address and the the size of the register region. + +Example: + + qcom,llcc@1100000 { + compatible = "qcom,sdm845-llcc"; + reg = <0x1100000 0x250000>; + };