| Message ID | 20180514221219.7091-28-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | softfloat patch roundup | expand |
Richard Henderson <richard.henderson@linaro.org> writes: > Reduce the number of ifdefs. Correct the result for OpenRISC > and TriCore (although TriCore fixed in target-specific code). > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > --- > fpu/softfloat-specialize.h | 21 ++++++++++++++------- > 1 file changed, 14 insertions(+), 7 deletions(-) > > diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h > index 9d562ed504..ec4fb6ba8b 100644 > --- a/fpu/softfloat-specialize.h > +++ b/fpu/softfloat-specialize.h > @@ -129,22 +129,29 @@ static FloatParts parts_default_nan(float_status *status) > uint64_t frac; > > #if defined(TARGET_SPARC) || defined(TARGET_M68K) > + /* !snan_bit_is_one, set all bits */ > frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1; > -#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \ > - defined(TARGET_S390X) || defined(TARGET_RISCV) > +#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ > + || defined(TARGET_MICROBLAZE) > + /* !snan_bit_is_one, set sign and msb */ > frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); > + sign = 1; > #elif defined(TARGET_HPPA) > + /* snan_bit_is_one, set msb-1. */ > frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); > #else > + /* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, > + * S390, SH4, TriCore, and Xtensa. I cannot find documentation > + * for Unicore32; the choice from the original commit is unchanged. > + * Our other supported targets, CRIS, LM32, Moxie, Nios2, and Tile, > + * do not have floating-point. > + */ > if (snan_bit_is_one(status)) { > + /* set all bits other than msb */ > frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; > } else { > -#if defined(TARGET_MIPS) > + /* set msb */ > frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); > -#else > - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); > - sign = 1; > -#endif > } > #endif -- Alex Bennée
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 9d562ed504..ec4fb6ba8b 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -129,22 +129,29 @@ static FloatParts parts_default_nan(float_status *status) uint64_t frac; #if defined(TARGET_SPARC) || defined(TARGET_M68K) + /* !snan_bit_is_one, set all bits */ frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1; -#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \ - defined(TARGET_S390X) || defined(TARGET_RISCV) +#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ + || defined(TARGET_MICROBLAZE) + /* !snan_bit_is_one, set sign and msb */ frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); + sign = 1; #elif defined(TARGET_HPPA) + /* snan_bit_is_one, set msb-1. */ frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); #else + /* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, + * S390, SH4, TriCore, and Xtensa. I cannot find documentation + * for Unicore32; the choice from the original commit is unchanged. + * Our other supported targets, CRIS, LM32, Moxie, Nios2, and Tile, + * do not have floating-point. + */ if (snan_bit_is_one(status)) { + /* set all bits other than msb */ frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; } else { -#if defined(TARGET_MIPS) + /* set msb */ frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); -#else - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); - sign = 1; -#endif } #endif
Reduce the number of ifdefs. Correct the result for OpenRISC and TriCore (although TriCore fixed in target-specific code). Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- fpu/softfloat-specialize.h | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-)