From patchwork Thu Apr 14 22:09:41 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Warren X-Patchwork-Id: 91308 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 1ED0EB6F94 for ; Fri, 15 Apr 2011 08:10:39 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 00939283C8; Fri, 15 Apr 2011 00:10:28 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id sNtaWoeuFO0n; Fri, 15 Apr 2011 00:10:27 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A07F6283D1; Fri, 15 Apr 2011 00:10:19 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BBB73283D0 for ; Fri, 15 Apr 2011 00:10:14 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id lMmRUo9H8+Yu for ; Fri, 15 Apr 2011 00:10:01 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pz0-f44.google.com (mail-pz0-f44.google.com [209.85.210.44]) by theia.denx.de (Postfix) with ESMTPS id 0DC94282E2 for ; Fri, 15 Apr 2011 00:09:58 +0200 (CEST) Received: by pzk30 with SMTP id 30so682492pzk.3 for ; Thu, 14 Apr 2011 15:09:56 -0700 (PDT) Received: by 10.68.40.133 with SMTP id x5mr824557pbk.381.1302818996528; Thu, 14 Apr 2011 15:09:56 -0700 (PDT) Received: from localhost.localdomain (ip70-190-110-83.ph.ph.cox.net [70.190.110.83]) by mx.google.com with ESMTPS id i5sm5208pbe.55.2011.04.14.15.09.55 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 14 Apr 2011 15:09:56 -0700 (PDT) From: Tom Warren To: u-boot@lists.denx.de Date: Thu, 14 Apr 2011 15:09:41 -0700 Message-Id: <1302818981-28270-4-git-send-email-twarren@nvidia.com> X-Mailer: git-send-email 1.7.4.3 In-Reply-To: <1302818981-28270-1-git-send-email-twarren@nvidia.com> References: <1302818981-28270-1-git-send-email-twarren@nvidia.com> Cc: twarren.nvidia@gmail.com, Tom Warren Subject: [U-Boot] [PATCH V2 3/3] arm: Tegra2: Move clk/mux init to board_early_init_f, add GPIO init X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Signed-off-by: Tom Warren --- board/nvidia/common/board.c | 32 +++++++++++++++-------- board/nvidia/common/board.h | 4 +++ board/nvidia/harmony/Makefile | 1 + board/nvidia/harmony/harmony.c | 34 ++++++++++++++++++++++++ board/nvidia/seaboard/Makefile | 1 + board/nvidia/seaboard/seaboard.c | 52 ++++++++++++++++++++++++++++++++++++++ 6 files changed, 113 insertions(+), 11 deletions(-) create mode 100644 board/nvidia/harmony/harmony.c create mode 100644 board/nvidia/seaboard/seaboard.c diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 5edd70f..3d6c248 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -41,7 +41,16 @@ const struct tegra2_sysinfo sysinfo = { #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { - debug("Board Early Init\n"); + /* Initialize periph clocks */ + clock_init(); + + /* Initialize periph pinmuxes */ + pinmux_init(); + + /* Initialize periph GPIOs */ + gpio_init(); + + /* Init UART, scratch regs, and start CPU */ tegra2_start(); return 0; } @@ -64,10 +73,10 @@ int timer_init(void) static void clock_init_uart(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - static int pllp_init_done; u32 reg; - if (!pllp_init_done) { + reg = readl(&clkrst->crc_pllp_base); + if (!(reg & PLL_BASE_OVRRIDE)) { /* Override pllp setup for 216MHz operation. */ reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP); reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM); @@ -78,8 +87,6 @@ static void clock_init_uart(void) reg &= ~PLL_BYPASS; writel(reg, &clkrst->crc_pllp_base); - - pllp_init_done++; } /* Now do the UART reset/clock enable */ @@ -182,6 +189,15 @@ void pinmux_init(void) } /* + * Routine: gpio_init + * Description: Do individual peripheral GPIO configs + */ +void gpio_init(void) +{ + gpio_config_uart(); +} + +/* * Routine: board_init * Description: Early hardware init. */ @@ -192,11 +208,5 @@ int board_init(void) /* board id for Linux */ gd->bd->bi_arch_number = CONFIG_MACH_TYPE; - /* Initialize peripheral clocks */ - clock_init(); - - /* Initialize periph pinmuxes */ - pinmux_init(); - return 0; } diff --git a/board/nvidia/common/board.h b/board/nvidia/common/board.h index 47c7885..350bc57 100644 --- a/board/nvidia/common/board.h +++ b/board/nvidia/common/board.h @@ -25,5 +25,9 @@ #define _BOARD_H_ void tegra2_start(void); +void clock_init(void); +void pinmux_init(void); +void gpio_init(void); +void gpio_config_uart(void); #endif /* BOARD_H */ diff --git a/board/nvidia/harmony/Makefile b/board/nvidia/harmony/Makefile index 3a146cb..9fb6b57 100644 --- a/board/nvidia/harmony/Makefile +++ b/board/nvidia/harmony/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +COBJS := $(BOARD).o COBJS += ../common/board.o SRCS := $(COBJS:.o=.c) diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c new file mode 100644 index 0000000..f1ab050 --- /dev/null +++ b/board/nvidia/harmony/harmony.c @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * Routine: gpio_config_uart + * Description: Does nothing on Harmony - no conflict w/SPI. + */ +void gpio_config_uart(void) +{ +} diff --git a/board/nvidia/seaboard/Makefile b/board/nvidia/seaboard/Makefile index 3a146cb..9fb6b57 100644 --- a/board/nvidia/seaboard/Makefile +++ b/board/nvidia/seaboard/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +COBJS := $(BOARD).o COBJS += ../common/board.o SRCS := $(COBJS:.o=.c) diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c new file mode 100644 index 0000000..4b9a8f3 --- /dev/null +++ b/board/nvidia/seaboard/seaboard.c @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* + * Routine: gpio_config_uart + * Description: Force GPIO_PI3 low on Seaboard so UART4 works. + */ +void gpio_config_uart(void) +{ + int gp = GPIO_PI3; + struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)]; + u32 val; + + /* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */ + val = readl(&bank->gpio_config[GPIO_PORT(gp)]); + val |= 1 << GPIO_BIT(gp); + writel(val, &bank->gpio_config[GPIO_PORT(gp)]); + + val = readl(&bank->gpio_out[GPIO_PORT(gp)]); + val &= ~(1 << GPIO_BIT(gp)); + writel(val, &bank->gpio_out[GPIO_PORT(gp)]); + + val = readl(&bank->gpio_dir_out[GPIO_PORT(gp)]); + val |= 1 << GPIO_BIT(gp); + writel(val, &bank->gpio_dir_out[GPIO_PORT(gp)]); +}