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[U-Boot,2/3] ARM: qemu-arm: Bump RAM size in AArch64 MMU table

Message ID 20180514154752.31081-2-tuomas.tynkkynen@iki.fi
State Accepted
Commit f37770c7707b9c11e1832005392a3b049b9fdf14
Delegated to: Tom Rini
Headers show
Series [U-Boot,1/3] PCI: dm: Ignore 64-bit memory regions if CONFIG_SYS_PCI_64BIT not set | expand

Commit Message

Tuomas Tynkkynen May 14, 2018, 3:47 p.m. UTC
Now that PCI devices work with highmem-enabled QEMU emulation, bump up
the RAM size in the MMU tables to gain access to the full 255 GB of RAM
potential instead of the puny 3 GB.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
---
 board/emulation/qemu-arm/qemu-arm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Simon Glass May 14, 2018, 7:51 p.m. UTC | #1
On 14 May 2018 at 09:47, Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> wrote:
> Now that PCI devices work with highmem-enabled QEMU emulation, bump up
> the RAM size in the MMU tables to gain access to the full 255 GB of RAM
> potential instead of the puny 3 GB.
>
> Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
> ---
>  board/emulation/qemu-arm/qemu-arm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini May 28, 2018, 7:12 p.m. UTC | #2
On Mon, May 14, 2018 at 06:47:51PM +0300, Tuomas Tynkkynen wrote:

> Now that PCI devices work with highmem-enabled QEMU emulation, bump up
> the RAM size in the MMU tables to gain access to the full 255 GB of RAM
> potential instead of the puny 3 GB.
> 
> Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
> Reviewed-by: Simon Glass <sjg@chromium.org>

Applied to u-boot/master, thanks!
diff mbox series

Patch

diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c
index 6ec4200170..085cbbef99 100644
--- a/board/emulation/qemu-arm/qemu-arm.c
+++ b/board/emulation/qemu-arm/qemu-arm.c
@@ -28,7 +28,7 @@  static struct mm_region qemu_arm64_mem_map[] = {
 		/* RAM */
 		.virt = 0x40000000UL,
 		.phys = 0x40000000UL,
-		.size = 0xc0000000UL,
+		.size = 255UL * SZ_1G,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
 	}, {