gpu: host1x: Acquire a reference to the IOVA cache

Message ID 20180514101301.32188-1-thierry.reding@gmail.com
State New
Headers show
Series
  • gpu: host1x: Acquire a reference to the IOVA cache
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Commit Message

Thierry Reding May 14, 2018, 10:13 a.m.
From: Thierry Reding <treding@nvidia.com>

The IOVA API uses a memory cache to allocate IOVA nodes from. To make
sure that this cache is available, obtain a reference to it and release
the reference when the cache is no longer needed.

On 64-bit ARM this is hidden by the fact that the DMA mapping API gets
that reference and never releases it. On 32-bit ARM, this is papered
over by the Tegra DRM driver (the sole user of the host1x API requiring
the cache) acquiring a reference to the IOVA cache for its own purposes.
However, there may be additional users of this API in the future, so fix
this upfront to avoid surprises.

Fixes: 404bfb78daf3 ("gpu: host1x: Add IOMMU support")
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/host1x/dev.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

Comments

Dmitry Osipenko May 14, 2018, 10:34 a.m. | #1
On 14.05.2018 13:13, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> The IOVA API uses a memory cache to allocate IOVA nodes from. To make
> sure that this cache is available, obtain a reference to it and release
> the reference when the cache is no longer needed.
> 
> On 64-bit ARM this is hidden by the fact that the DMA mapping API gets
> that reference and never releases it. On 32-bit ARM, this is papered
> over by the Tegra DRM driver (the sole user of the host1x API requiring
> the cache) acquiring a reference to the IOVA cache for its own purposes.
> However, there may be additional users of this API in the future, so fix
> this upfront to avoid surprises.
> 
> Fixes: 404bfb78daf3 ("gpu: host1x: Add IOMMU support")
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  drivers/gpu/host1x/dev.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
> index 03db71173f5d..f1d5f76e9c33 100644
> --- a/drivers/gpu/host1x/dev.c
> +++ b/drivers/gpu/host1x/dev.c
> @@ -223,10 +223,14 @@ static int host1x_probe(struct platform_device *pdev)
>  		struct iommu_domain_geometry *geometry;
>  		unsigned long order;
>  
> +		err = iova_cache_get();
> +		if (err < 0)
> +			goto put_group;
> +
>  		host->domain = iommu_domain_alloc(&platform_bus_type);
>  		if (!host->domain) {
>  			err = -ENOMEM;
> -			goto put_group;
> +			goto put_cache;
>  		}
>  
>  		err = iommu_attach_group(host->domain, host->group);
> @@ -234,6 +238,7 @@ static int host1x_probe(struct platform_device *pdev)
>  			if (err == -ENODEV) {
>  				iommu_domain_free(host->domain);
>  				host->domain = NULL;
> +				iova_cache_put();
>  				iommu_group_put(host->group);
>  				host->group = NULL;
>  				goto skip_iommu;
> @@ -308,6 +313,9 @@ static int host1x_probe(struct platform_device *pdev)
>  fail_free_domain:
>  	if (host->domain)
>  		iommu_domain_free(host->domain);
> +put_cache:
> +	if (host->group)
> +		iova_cache_put();
>  put_group:
>  	iommu_group_put(host->group);
>  
> @@ -328,6 +336,7 @@ static int host1x_remove(struct platform_device *pdev)
>  		put_iova_domain(&host->iova);
>  		iommu_detach_group(host->domain, host->group);
>  		iommu_domain_free(host->domain);
> +		iova_cache_put();
>  		iommu_group_put(host->group);
>  	}
>  
> 

Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
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Thierry Reding May 14, 2018, 10:57 a.m. | #2
On Mon, May 14, 2018 at 01:34:27PM +0300, Dmitry Osipenko wrote:
> On 14.05.2018 13:13, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> > 
> > The IOVA API uses a memory cache to allocate IOVA nodes from. To make
> > sure that this cache is available, obtain a reference to it and release
> > the reference when the cache is no longer needed.
> > 
> > On 64-bit ARM this is hidden by the fact that the DMA mapping API gets
> > that reference and never releases it. On 32-bit ARM, this is papered
> > over by the Tegra DRM driver (the sole user of the host1x API requiring
> > the cache) acquiring a reference to the IOVA cache for its own purposes.
> > However, there may be additional users of this API in the future, so fix
> > this upfront to avoid surprises.
> > 
> > Fixes: 404bfb78daf3 ("gpu: host1x: Add IOMMU support")
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> >  drivers/gpu/host1x/dev.c | 11 ++++++++++-
> >  1 file changed, 10 insertions(+), 1 deletion(-)

Applied, thanks.

Thierry

Patch

diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index 03db71173f5d..f1d5f76e9c33 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -223,10 +223,14 @@  static int host1x_probe(struct platform_device *pdev)
 		struct iommu_domain_geometry *geometry;
 		unsigned long order;
 
+		err = iova_cache_get();
+		if (err < 0)
+			goto put_group;
+
 		host->domain = iommu_domain_alloc(&platform_bus_type);
 		if (!host->domain) {
 			err = -ENOMEM;
-			goto put_group;
+			goto put_cache;
 		}
 
 		err = iommu_attach_group(host->domain, host->group);
@@ -234,6 +238,7 @@  static int host1x_probe(struct platform_device *pdev)
 			if (err == -ENODEV) {
 				iommu_domain_free(host->domain);
 				host->domain = NULL;
+				iova_cache_put();
 				iommu_group_put(host->group);
 				host->group = NULL;
 				goto skip_iommu;
@@ -308,6 +313,9 @@  static int host1x_probe(struct platform_device *pdev)
 fail_free_domain:
 	if (host->domain)
 		iommu_domain_free(host->domain);
+put_cache:
+	if (host->group)
+		iova_cache_put();
 put_group:
 	iommu_group_put(host->group);
 
@@ -328,6 +336,7 @@  static int host1x_remove(struct platform_device *pdev)
 		put_iova_domain(&host->iova);
 		iommu_detach_group(host->domain, host->group);
 		iommu_domain_free(host->domain);
+		iova_cache_put();
 		iommu_group_put(host->group);
 	}