From patchwork Thu Apr 14 17:56:25 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 91271 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 015691007D5 for ; Fri, 15 Apr 2011 03:57:53 +1000 (EST) Received: (qmail 4908 invoked by alias); 14 Apr 2011 17:57:44 -0000 Received: (qmail 4695 invoked by uid 22791); 14 Apr 2011 17:57:30 -0000 X-SWARE-Spam-Status: No, hits=0.4 required=5.0 tests=AWL, BAYES_50, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SARE_HTML_INV_TAG, TW_AV, TW_VX, TW_XV, TW_ZJ, T_TO_NO_BRKTS_FREEMAIL X-Spam-Check-By: sourceware.org Received: from mail-pv0-f175.google.com (HELO mail-pv0-f175.google.com) (74.125.83.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 14 Apr 2011 17:57:16 +0000 Received: by pvc30 with SMTP id 30so827238pvc.20 for ; Thu, 14 Apr 2011 10:56:55 -0700 (PDT) MIME-Version: 1.0 Received: by 10.68.6.67 with SMTP id y3mr669955pby.12.1302803815134; Thu, 14 Apr 2011 10:56:55 -0700 (PDT) Received: by 10.142.87.14 with HTTP; Thu, 14 Apr 2011 10:56:25 -0700 (PDT) Date: Thu, 14 Apr 2011 19:56:25 +0200 Message-ID: Subject: [PATCH 8/n, i386]: Merge SSE and AVX patterns using "enable" attribute. From: Uros Bizjak To: gcc-patches@gcc.gnu.org Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hello! Attached patch converts "Intel SSE4.1 instructions" and remaining sections. 2011-04-14 Uros Bizjak * config/i386/sse.md (sse4_1): New mode attribute. (_blend): Macroize from avx_blend and sse4_1_blend using VF mode iterator. (_blendv): Macroize from avx_blendv and sse4_1_blendv using VF mode iterator. (_dp): Macroize from avx_dp and sse4_1_dp using VF mode iterator. (sse4_1_mpsadbw): Merge with *avx_mpsadbw. (sse4_1_packusdw): Merge with *avx_packusdw. (sse4_1_pblendvb): Merge with *avx_pblendvb. (sse4_1_pblendw): Merge with *avx_pblendw. (avx_vtest): Use VF mode iterator. (_round): Macroize from avx_round256 and sse4_1_round using VF mode iterator. (sse4_1_round): Merge with *avx_round. (aesenc): Merge with *avx_aesenc. (aesenclast): Merge with *avx_aesenclast. (aesdec): Merge with *avx_aesdec. (aesdeclast): Merge with *avx_aesdeclast. (pclmulqdq): Merge with *pclmulqdq. * config/i386/predicates.md (reg_not_xmm0_operand_maybe_avx): New predicate. (nonimm_not_xmm0_operand_maybe_avx): Ditto. Bootstrapped and regression tested on x86_64-pc-linux-gnu {,-m32} AVX target. Uros. Index: predicates.md =================================================================== --- predicates.md (revision 172436) +++ predicates.md (working copy) @@ -106,11 +106,23 @@ return !REG_P (op) || REGNO (op) != FIRST_SSE_REG; }) -;; As above, but allow nonimmediate operands. +;; As above, but also allow memory operands. (define_predicate "nonimm_not_xmm0_operand" (ior (match_operand 0 "memory_operand") (match_operand 0 "reg_not_xmm0_operand"))) +;; Return true if op is not xmm0 register, but only for non-AVX targets. +(define_predicate "reg_not_xmm0_operand_maybe_avx" + (if_then_else (match_test "TARGET_AVX") + (match_operand 0 "register_operand") + (match_operand 0 "reg_not_xmm0_operand"))) + +;; As above, but also allow memory operands. +(define_predicate "nonimm_not_xmm0_operand_maybe_avx" + (if_then_else (match_test "TARGET_AVX") + (match_operand 0 "nonimmediate_operand") + (match_operand 0 "nonimm_not_xmm0_operand"))) + ;; Return true if VALUE can be stored in a sign extended immediate field. (define_predicate "x86_64_immediate_operand" (match_code "const_int,symbol_ref,label_ref,const") Index: sse.md =================================================================== --- sse.md (revision 172436) +++ sse.md (working copy) @@ -124,6 +124,10 @@ (V4SF "sse") (V2DF "sse2") (V8SF "avx") (V4DF "avx")]) +(define_mode_attr sse4_1 + [(V4SF "sse4_1") (V2DF "sse4_1") + (V8SF "avx") (V4DF "avx")]) + ;; Mapping from integer vector mode to mnemonic suffix (define_mode_attr ssevecsize [(V16QI "b") (V8HI "w") (V4SI "d") (V2DI "q")]) @@ -8124,91 +8128,60 @@ ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(define_insn "avx_blend" - [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x") - (vec_merge:AVXMODEF2P - (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm") - (match_operand:AVXMODEF2P 1 "register_operand" "x") - (match_operand:SI 3 "const_0_to__operand" "n")))] - "TARGET_AVX" - "vblend\t{%3, %2, %1, %0|%0, %1, %2, %3}" - [(set_attr "type" "ssemov") - (set_attr "prefix_extra" "1") - (set_attr "length_immediate" "1") - (set_attr "prefix" "vex") - (set_attr "mode" "")]) - -(define_insn "avx_blendv" - [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x") - (unspec:AVXMODEF2P - [(match_operand:AVXMODEF2P 1 "register_operand" "x") - (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm") - (match_operand:AVXMODEF2P 3 "register_operand" "x")] - UNSPEC_BLENDV))] - "TARGET_AVX" - "vblendv\t{%3, %2, %1, %0|%0, %1, %2, %3}" - [(set_attr "type" "ssemov") - (set_attr "prefix_extra" "1") - (set_attr "length_immediate" "1") - (set_attr "prefix" "vex") - (set_attr "mode" "")]) - -(define_insn "sse4_1_blend" - [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") - (vec_merge:SSEMODEF2P - (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm") - (match_operand:SSEMODEF2P 1 "register_operand" "0") - (match_operand:SI 3 "const_0_to__operand" "n")))] +(define_insn "_blend" + [(set (match_operand:VF 0 "register_operand" "=x,x") + (vec_merge:VF + (match_operand:VF 2 "nonimmediate_operand" "xm,xm") + (match_operand:VF 1 "register_operand" "0,x") + (match_operand:SI 3 "const_0_to__operand" "n,n")))] "TARGET_SSE4_1" - "blend\t{%3, %2, %0|%0, %2, %3}" - [(set_attr "type" "ssemov") - (set_attr "prefix_data16" "1") - (set_attr "prefix_extra" "1") + "@ + blend\t{%3, %2, %0|%0, %2, %3} + vblend\t{%3, %2, %1, %0|%0, %1, %2, %3}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "ssemov") (set_attr "length_immediate" "1") + (set_attr "prefix_data16" "1,*") + (set_attr "prefix_extra" "1") + (set_attr "prefix" "orig,vex") (set_attr "mode" "")]) -(define_insn "sse4_1_blendv" - [(set (match_operand:SSEMODEF2P 0 "reg_not_xmm0_operand" "=x") - (unspec:SSEMODEF2P - [(match_operand:SSEMODEF2P 1 "reg_not_xmm0_operand" "0") - (match_operand:SSEMODEF2P 2 "nonimm_not_xmm0_operand" "xm") - (match_operand:SSEMODEF2P 3 "register_operand" "Yz")] +(define_insn "_blendv" + [(set (match_operand:VF 0 "reg_not_xmm0_operand_maybe_avx" "=x,x") + (unspec:VF + [(match_operand:VF 1 "reg_not_xmm0_operand_maybe_avx" "0,x") + (match_operand:VF 2 "nonimm_not_xmm0_operand_maybe_avx" "xm,xm") + (match_operand:VF 3 "register_operand" "Yz,x")] UNSPEC_BLENDV))] "TARGET_SSE4_1" - "blendv\t{%3, %2, %0|%0, %2, %3}" - [(set_attr "type" "ssemov") - (set_attr "prefix_data16" "1") + "@ + blendv\t{%3, %2, %0|%0, %2, %3} + vblendv\t{%3, %2, %1, %0|%0, %1, %2, %3}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "ssemov") + (set_attr "length_immediate" "1") + (set_attr "prefix_data16" "1,*") (set_attr "prefix_extra" "1") + (set_attr "prefix" "orig,vex") (set_attr "mode" "")]) -(define_insn "avx_dp" - [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x") - (unspec:AVXMODEF2P - [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x") - (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm") - (match_operand:SI 3 "const_0_to_255_operand" "n")] +(define_insn "_dp" + [(set (match_operand:VF 0 "register_operand" "=x,x") + (unspec:VF + [(match_operand:VF 1 "nonimmediate_operand" "%0,x") + (match_operand:VF 2 "nonimmediate_operand" "xm,xm") + (match_operand:SI 3 "const_0_to_255_operand" "n,n")] UNSPEC_DP))] - "TARGET_AVX" - "vdp\t{%3, %2, %1, %0|%0, %1, %2, %3}" - [(set_attr "type" "ssemul") - (set_attr "prefix" "vex") - (set_attr "prefix_extra" "1") - (set_attr "length_immediate" "1") - (set_attr "mode" "")]) - -(define_insn "sse4_1_dp" - [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") - (unspec:SSEMODEF2P - [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0") - (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm") - (match_operand:SI 3 "const_0_to_255_operand" "n")] - UNSPEC_DP))] "TARGET_SSE4_1" - "dp\t{%3, %2, %0|%0, %2, %3}" - [(set_attr "type" "ssemul") - (set_attr "prefix_data16" "1") - (set_attr "prefix_extra" "1") + "@ + dp\t{%3, %2, %0|%0, %2, %3} + vdp\t{%3, %2, %1, %0|%0, %1, %2, %3}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "ssemul") (set_attr "length_immediate" "1") + (set_attr "prefix_data16" "1,*") + (set_attr "prefix_extra" "1") + (set_attr "prefix" "orig,vex") (set_attr "mode" "")]) (define_insn "sse4_1_movntdqa" @@ -8222,111 +8195,73 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "TI")]) -(define_insn "*avx_mpsadbw" - [(set (match_operand:V16QI 0 "register_operand" "=x") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x") - (match_operand:V16QI 2 "nonimmediate_operand" "xm") - (match_operand:SI 3 "const_0_to_255_operand" "n")] - UNSPEC_MPSADBW))] - "TARGET_AVX" - "vmpsadbw\t{%3, %2, %1, %0|%0, %1, %2, %3}" - [(set_attr "type" "sselog1") - (set_attr "prefix" "vex") - (set_attr "prefix_extra" "1") - (set_attr "length_immediate" "1") - (set_attr "mode" "TI")]) - (define_insn "sse4_1_mpsadbw" - [(set (match_operand:V16QI 0 "register_operand" "=x") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0") - (match_operand:V16QI 2 "nonimmediate_operand" "xm") - (match_operand:SI 3 "const_0_to_255_operand" "n")] + [(set (match_operand:V16QI 0 "register_operand" "=x,x") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0,x") + (match_operand:V16QI 2 "nonimmediate_operand" "xm,xm") + (match_operand:SI 3 "const_0_to_255_operand" "n,n")] UNSPEC_MPSADBW))] "TARGET_SSE4_1" - "mpsadbw\t{%3, %2, %0|%0, %2, %3}" - [(set_attr "type" "sselog1") - (set_attr "prefix_extra" "1") + "@ + mpsadbw\t{%3, %2, %0|%0, %2, %3} + vmpsadbw\t{%3, %2, %1, %0|%0, %1, %2, %3}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sselog1") (set_attr "length_immediate" "1") - (set_attr "mode" "TI")]) - -(define_insn "*avx_packusdw" - [(set (match_operand:V8HI 0 "register_operand" "=x") - (vec_concat:V8HI - (us_truncate:V4HI - (match_operand:V4SI 1 "register_operand" "x")) - (us_truncate:V4HI - (match_operand:V4SI 2 "nonimmediate_operand" "xm"))))] - "TARGET_AVX" - "vpackusdw\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "type" "sselog") (set_attr "prefix_extra" "1") - (set_attr "prefix" "vex") + (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) (define_insn "sse4_1_packusdw" - [(set (match_operand:V8HI 0 "register_operand" "=x") + [(set (match_operand:V8HI 0 "register_operand" "=x,x") (vec_concat:V8HI (us_truncate:V4HI - (match_operand:V4SI 1 "register_operand" "0")) + (match_operand:V4SI 1 "register_operand" "0,x")) (us_truncate:V4HI - (match_operand:V4SI 2 "nonimmediate_operand" "xm"))))] + (match_operand:V4SI 2 "nonimmediate_operand" "xm,xm"))))] "TARGET_SSE4_1" - "packusdw\t{%2, %0|%0, %2}" - [(set_attr "type" "sselog") + "@ + packusdw\t{%2, %0|%0, %2} + vpackusdw\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sselog") (set_attr "prefix_extra" "1") + (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) -(define_insn "*avx_pblendvb" - [(set (match_operand:V16QI 0 "register_operand" "=x") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x") - (match_operand:V16QI 2 "nonimmediate_operand" "xm") - (match_operand:V16QI 3 "register_operand" "x")] - UNSPEC_BLENDV))] - "TARGET_AVX" - "vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}" - [(set_attr "type" "ssemov") - (set_attr "prefix_extra" "1") - (set_attr "length_immediate" "1") - (set_attr "prefix" "vex") - (set_attr "mode" "TI")]) - (define_insn "sse4_1_pblendvb" - [(set (match_operand:V16QI 0 "reg_not_xmm0_operand" "=x") - (unspec:V16QI [(match_operand:V16QI 1 "reg_not_xmm0_operand" "0") - (match_operand:V16QI 2 "nonimm_not_xmm0_operand" "xm") - (match_operand:V16QI 3 "register_operand" "Yz")] - UNSPEC_BLENDV))] + [(set (match_operand:V16QI 0 "reg_not_xmm0_operand" "=x,x") + (unspec:V16QI + [(match_operand:V16QI 1 "reg_not_xmm0_operand_maybe_avx" "0,x") + (match_operand:V16QI 2 "nonimm_not_xmm0_operand_maybe_avx" "xm,xm") + (match_operand:V16QI 3 "register_operand" "Yz,x")] + UNSPEC_BLENDV))] "TARGET_SSE4_1" - "pblendvb\t{%3, %2, %0|%0, %2, %3}" - [(set_attr "type" "ssemov") + "@ + pblendvb\t{%3, %2, %0|%0, %2, %3} + vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") + (set_attr "length_immediate" "*,1") + (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) -(define_insn "*avx_pblendw" - [(set (match_operand:V8HI 0 "register_operand" "=x") - (vec_merge:V8HI - (match_operand:V8HI 2 "nonimmediate_operand" "xm") - (match_operand:V8HI 1 "register_operand" "x") - (match_operand:SI 3 "const_0_to_255_operand" "n")))] - "TARGET_AVX" - "vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}" - [(set_attr "type" "ssemov") - (set_attr "prefix" "vex") - (set_attr "prefix_extra" "1") - (set_attr "length_immediate" "1") - (set_attr "mode" "TI")]) - (define_insn "sse4_1_pblendw" - [(set (match_operand:V8HI 0 "register_operand" "=x") + [(set (match_operand:V8HI 0 "register_operand" "=x,x") (vec_merge:V8HI - (match_operand:V8HI 2 "nonimmediate_operand" "xm") - (match_operand:V8HI 1 "register_operand" "0") - (match_operand:SI 3 "const_0_to_255_operand" "n")))] + (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm") + (match_operand:V8HI 1 "register_operand" "0,x") + (match_operand:SI 3 "const_0_to_255_operand" "n,n")))] "TARGET_SSE4_1" - "pblendw\t{%3, %2, %0|%0, %2, %3}" - [(set_attr "type" "ssemov") + "@ + pblendw\t{%3, %2, %0|%0, %2, %3} + vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") + (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) (define_insn "sse4_1_phminposuw" @@ -8438,8 +8373,8 @@ ;; setting FLAGS_REG. But it is not a really compare instruction. (define_insn "avx_vtest" [(set (reg:CC FLAGS_REG) - (unspec:CC [(match_operand:AVXMODEF2P 0 "register_operand" "x") - (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "xm")] + (unspec:CC [(match_operand:VF 0 "register_operand" "x") + (match_operand:VF 1 "nonimmediate_operand" "xm")] UNSPEC_VTESTP))] "TARGET_AVX" "vtest\t{%1, %0|%0, %1}" @@ -8474,67 +8409,44 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "TI")]) -(define_insn "avx_round256" - [(set (match_operand:AVX256MODEF2P 0 "register_operand" "=x") - (unspec:AVX256MODEF2P - [(match_operand:AVX256MODEF2P 1 "nonimmediate_operand" "xm") +(define_insn "_round" + [(set (match_operand:VF 0 "register_operand" "=x") + (unspec:VF + [(match_operand:VF 1 "nonimmediate_operand" "xm") (match_operand:SI 2 "const_0_to_15_operand" "n")] UNSPEC_ROUND))] - "TARGET_AVX" - "vround\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "type" "ssecvt") - (set_attr "prefix_extra" "1") - (set_attr "length_immediate" "1") - (set_attr "prefix" "vex") - (set_attr "mode" "")]) - -(define_insn "sse4_1_round" - [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") - (unspec:SSEMODEF2P - [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm") - (match_operand:SI 2 "const_0_to_15_operand" "n")] - UNSPEC_ROUND))] "TARGET_ROUND" "%vround\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ssecvt") - (set_attr "prefix_data16" "1") + (set (attr "prefix_data16") + (if_then_else + (ne (symbol_ref "TARGET_AVX") (const_int 0)) + (const_string "*") + (const_string "1"))) (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex") (set_attr "mode" "")]) -(define_insn "*avx_round" - [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") - (vec_merge:SSEMODEF2P - (unspec:SSEMODEF2P - [(match_operand:SSEMODEF2P 2 "register_operand" "x") - (match_operand:SI 3 "const_0_to_15_operand" "n")] - UNSPEC_ROUND) - (match_operand:SSEMODEF2P 1 "register_operand" "x") - (const_int 1)))] - "TARGET_AVX" - "vround\t{%3, %2, %1, %0|%0, %1, %2, %3}" - [(set_attr "type" "ssecvt") - (set_attr "prefix_extra" "1") - (set_attr "length_immediate" "1") - (set_attr "prefix" "vex") - (set_attr "mode" "")]) - (define_insn "sse4_1_round" - [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") - (vec_merge:SSEMODEF2P - (unspec:SSEMODEF2P - [(match_operand:SSEMODEF2P 2 "register_operand" "x") - (match_operand:SI 3 "const_0_to_15_operand" "n")] + [(set (match_operand:VF_128 0 "register_operand" "=x,x") + (vec_merge:VF_128 + (unspec:VF_128 + [(match_operand:VF_128 2 "register_operand" "x,x") + (match_operand:SI 3 "const_0_to_15_operand" "n,n")] UNSPEC_ROUND) - (match_operand:SSEMODEF2P 1 "register_operand" "0") + (match_operand:VF_128 1 "register_operand" "0,x") (const_int 1)))] "TARGET_ROUND" - "round\t{%3, %2, %0|%0, %2, %3}" - [(set_attr "type" "ssecvt") - (set_attr "prefix_data16" "1") - (set_attr "prefix_extra" "1") + "@ + round\t{%3, %2, %0|%0, %2, %3} + vround\t{%3, %2, %1, %0|%0, %1, %2, %3}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "ssecvt") (set_attr "length_immediate" "1") + (set_attr "prefix_data16" "1,*") + (set_attr "prefix_extra" "1") + (set_attr "prefix" "orig,vex") (set_attr "mode" "")]) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -10084,96 +9996,65 @@ (set_attr "mode" "")]) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(define_insn "*avx_aesenc" - [(set (match_operand:V2DI 0 "register_operand" "=x") - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x") - (match_operand:V2DI 2 "nonimmediate_operand" "xm")] - UNSPEC_AESENC))] - "TARGET_AES && TARGET_AVX" - "vaesenc\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "type" "sselog1") - (set_attr "prefix_extra" "1") - (set_attr "prefix" "vex") - (set_attr "mode" "TI")]) (define_insn "aesenc" - [(set (match_operand:V2DI 0 "register_operand" "=x") - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0") - (match_operand:V2DI 2 "nonimmediate_operand" "xm")] + [(set (match_operand:V2DI 0 "register_operand" "=x,x") + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x") + (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")] UNSPEC_AESENC))] "TARGET_AES" - "aesenc\t{%2, %0|%0, %2}" - [(set_attr "type" "sselog1") + "@ + aesenc\t{%2, %0|%0, %2} + vaesenc\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sselog1") (set_attr "prefix_extra" "1") + (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) -(define_insn "*avx_aesenclast" - [(set (match_operand:V2DI 0 "register_operand" "=x") - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x") - (match_operand:V2DI 2 "nonimmediate_operand" "xm")] - UNSPEC_AESENCLAST))] - "TARGET_AES && TARGET_AVX" - "vaesenclast\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "type" "sselog1") - (set_attr "prefix_extra" "1") - (set_attr "prefix" "vex") - (set_attr "mode" "TI")]) - (define_insn "aesenclast" - [(set (match_operand:V2DI 0 "register_operand" "=x") - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0") - (match_operand:V2DI 2 "nonimmediate_operand" "xm")] + [(set (match_operand:V2DI 0 "register_operand" "=x,x") + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x") + (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")] UNSPEC_AESENCLAST))] "TARGET_AES" - "aesenclast\t{%2, %0|%0, %2}" - [(set_attr "type" "sselog1") + "@ + aesenclast\t{%2, %0|%0, %2} + vaesenclast\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sselog1") (set_attr "prefix_extra" "1") + (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) -(define_insn "*avx_aesdec" - [(set (match_operand:V2DI 0 "register_operand" "=x") - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x") - (match_operand:V2DI 2 "nonimmediate_operand" "xm")] - UNSPEC_AESDEC))] - "TARGET_AES && TARGET_AVX" - "vaesdec\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "type" "sselog1") - (set_attr "prefix_extra" "1") - (set_attr "prefix" "vex") - (set_attr "mode" "TI")]) - (define_insn "aesdec" - [(set (match_operand:V2DI 0 "register_operand" "=x") - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0") - (match_operand:V2DI 2 "nonimmediate_operand" "xm")] + [(set (match_operand:V2DI 0 "register_operand" "=x,x") + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x") + (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")] UNSPEC_AESDEC))] "TARGET_AES" - "aesdec\t{%2, %0|%0, %2}" - [(set_attr "type" "sselog1") + "@ + aesdec\t{%2, %0|%0, %2} + vaesdec\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sselog1") (set_attr "prefix_extra" "1") + (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) -(define_insn "*avx_aesdeclast" - [(set (match_operand:V2DI 0 "register_operand" "=x") - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x") - (match_operand:V2DI 2 "nonimmediate_operand" "xm")] - UNSPEC_AESDECLAST))] - "TARGET_AES && TARGET_AVX" - "vaesdeclast\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "type" "sselog1") - (set_attr "prefix_extra" "1") - (set_attr "prefix" "vex") - (set_attr "mode" "TI")]) - (define_insn "aesdeclast" - [(set (match_operand:V2DI 0 "register_operand" "=x") - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0") - (match_operand:V2DI 2 "nonimmediate_operand" "xm")] + [(set (match_operand:V2DI 0 "register_operand" "=x,x") + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x") + (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")] UNSPEC_AESDECLAST))] "TARGET_AES" - "aesdeclast\t{%2, %0|%0, %2}" - [(set_attr "type" "sselog1") + "@ + aesdeclast\t{%2, %0|%0, %2} + vaesdeclast\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sselog1") (set_attr "prefix_extra" "1") + (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) (define_insn "aesimc" @@ -10200,31 +10081,21 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "TI")]) -(define_insn "*vpclmulqdq" - [(set (match_operand:V2DI 0 "register_operand" "=x") - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x") - (match_operand:V2DI 2 "nonimmediate_operand" "xm") - (match_operand:SI 3 "const_0_to_255_operand" "n")] - UNSPEC_PCLMUL))] - "TARGET_PCLMUL && TARGET_AVX" - "vpclmulqdq\t{%3, %2, %1, %0|%0, %1, %2, %3}" - [(set_attr "type" "sselog1") - (set_attr "prefix_extra" "1") - (set_attr "length_immediate" "1") - (set_attr "prefix" "vex") - (set_attr "mode" "TI")]) - (define_insn "pclmulqdq" - [(set (match_operand:V2DI 0 "register_operand" "=x") - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0") - (match_operand:V2DI 2 "nonimmediate_operand" "xm") - (match_operand:SI 3 "const_0_to_255_operand" "n")] + [(set (match_operand:V2DI 0 "register_operand" "=x,x") + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x") + (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm") + (match_operand:SI 3 "const_0_to_255_operand" "n,n")] UNSPEC_PCLMUL))] "TARGET_PCLMUL" - "pclmulqdq\t{%3, %2, %0|%0, %2, %3}" - [(set_attr "type" "sselog1") + "@ + pclmulqdq\t{%3, %2, %0|%0, %2, %3} + vpclmulqdq\t{%3, %2, %1, %0|%0, %1, %2, %3}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") + (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) (define_expand "avx_vzeroall"