Patchwork [U-Boot] MPC83xx: add config options for memory setup.

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Submitter Andre Schwarz
Date April 14, 2011, 12:54 p.m.
Message ID <1302785645-14555-1-git-send-email-andre.schwarz@matrix-vision.de>
Download mbox | patch
Permalink /patch/91229/
State Accepted
Commit 03c0a9244098e02a3d076418d6a23a3abd117ad9
Delegated to: Kim Phillips
Headers show

Comments

Andre Schwarz - April 14, 2011, 12:54 p.m.
CPO value and driver strength settings are board specifc.
Also allow SPD data fetch from any accessible I2C EEPROM.

Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
---
 arch/powerpc/cpu/mpc83xx/spd_sdram.c |   19 ++++++++++++++++++-
 1 files changed, 18 insertions(+), 1 deletions(-)
York Sun - April 18, 2011, 12:10 a.m.
On Thu, 2011-04-14 at 14:54 +0200, Andre Schwarz wrote:
> CPO value and driver strength settings are board specifc.
> Also allow SPD data fetch from any accessible I2C EEPROM.
> 
> Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
> ---
>  arch/powerpc/cpu/mpc83xx/spd_sdram.c |   19 ++++++++++++++++++-
>  1 files changed, 18 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
> index 44aaa9a..9b01f0d 100644
> --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
> +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
> @@ -68,6 +68,12 @@ void board_add_ram_info(int use_default)
>  #ifndef	CONFIG_SYS_READ_SPD
>  #define CONFIG_SYS_READ_SPD	i2c_read
>  #endif
> +#ifndef SPD_EEPROM_OFFSET
> +#define SPD_EEPROM_OFFSET	0
> +#endif
> +#ifndef SPD_EEPROM_ADDR_LEN
> +#define SPD_EEPROM_ADDR_LEN     1
> +#endif
>  
>  /*
>   * Convert picoseconds into clock cycles (rounding up if needed).
> @@ -160,7 +166,8 @@ long int spd_sdram()
>  	isync();
>  
>  	/* Read SPD parameters with I2C */
> -	CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
> +	CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, SPD_EEPROM_OFFSET,
> +		SPD_EEPROM_ADDR_LEN, (uchar *) &spd, sizeof(spd));
>  #ifdef SPD_DEBUG
>  	spd_debug(&spd);
>  #endif
> @@ -562,6 +569,9 @@ long int spd_sdram()
>  	 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
>  	 */
>  	wr_data_delay = 2;
> +#ifdef CONFIG_SYS_DDR_WRITE_DATA_DELAY
> +	wr_data_delay = CONFIG_SYS_DDR_WRITE_DATA_DELAY;
> +#endif
>  
>  	/*
>  	 * Write Latency
> @@ -601,6 +611,9 @@ long int spd_sdram()
>  	 */
>  	cpo = 0;
>  	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
> +#ifdef CONFIG_SYS_DDR_CPO
> +		cpo = CONFIG_SYS_DDR_CPO;
> +#else
>  		if (effective_data_rate == 266) {
>  			cpo = 0x4;		/* READ_LAT + 1/2 */
>  		} else if (effective_data_rate == 333) {
> @@ -611,6 +624,7 @@ long int spd_sdram()
>  			/* Automatic calibration */
>  			cpo = 0x1f;
>  		}
> +#endif
>  	}
>  
>  	ddr->timing_cfg_2 = (0
> @@ -679,6 +693,9 @@ long int spd_sdram()
>  		ddr->sdram_mode =
>  			(0
>  			 | (1 << (16 + 10))             /* DQS Differential disable */
> +#ifdef CONFIG_SYS_DDR_MODE_WEAK
> +			 | (1 << (16 + 1))		/* weak driver (~60%) */
> +#endif
>  			 | (add_lat << (16 + 3))        /* Additive Latency in EMRS1 */
>  			 | (mode_odt_enable << 16)      /* ODT Enable in EMRS1 */
>  			 | ((twr_clk - 1) << 9)         /* Write Recovery Autopre */

Looks good to me.

Acked-by: York Sun <yorksun@freescale.com>
Kim Phillips - July 7, 2011, 12:14 a.m.
On Mon, 18 Apr 2011 08:10:12 +0800
York Sun <yorksun@freescale.com> wrote:

> On Thu, 2011-04-14 at 14:54 +0200, Andre Schwarz wrote:
> > CPO value and driver strength settings are board specifc.
> > Also allow SPD data fetch from any accessible I2C EEPROM.
> > 
> > Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
> > ---
> Looks good to me.
> 
> Acked-by: York Sun <yorksun@freescale.com>

applied to u-boot-mpc83xx.

Thanks,

Kim

Patch

diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
index 44aaa9a..9b01f0d 100644
--- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
+++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
@@ -68,6 +68,12 @@  void board_add_ram_info(int use_default)
 #ifndef	CONFIG_SYS_READ_SPD
 #define CONFIG_SYS_READ_SPD	i2c_read
 #endif
+#ifndef SPD_EEPROM_OFFSET
+#define SPD_EEPROM_OFFSET	0
+#endif
+#ifndef SPD_EEPROM_ADDR_LEN
+#define SPD_EEPROM_ADDR_LEN     1
+#endif
 
 /*
  * Convert picoseconds into clock cycles (rounding up if needed).
@@ -160,7 +166,8 @@  long int spd_sdram()
 	isync();
 
 	/* Read SPD parameters with I2C */
-	CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
+	CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, SPD_EEPROM_OFFSET,
+		SPD_EEPROM_ADDR_LEN, (uchar *) &spd, sizeof(spd));
 #ifdef SPD_DEBUG
 	spd_debug(&spd);
 #endif
@@ -562,6 +569,9 @@  long int spd_sdram()
 	 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
 	 */
 	wr_data_delay = 2;
+#ifdef CONFIG_SYS_DDR_WRITE_DATA_DELAY
+	wr_data_delay = CONFIG_SYS_DDR_WRITE_DATA_DELAY;
+#endif
 
 	/*
 	 * Write Latency
@@ -601,6 +611,9 @@  long int spd_sdram()
 	 */
 	cpo = 0;
 	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+#ifdef CONFIG_SYS_DDR_CPO
+		cpo = CONFIG_SYS_DDR_CPO;
+#else
 		if (effective_data_rate == 266) {
 			cpo = 0x4;		/* READ_LAT + 1/2 */
 		} else if (effective_data_rate == 333) {
@@ -611,6 +624,7 @@  long int spd_sdram()
 			/* Automatic calibration */
 			cpo = 0x1f;
 		}
+#endif
 	}
 
 	ddr->timing_cfg_2 = (0
@@ -679,6 +693,9 @@  long int spd_sdram()
 		ddr->sdram_mode =
 			(0
 			 | (1 << (16 + 10))             /* DQS Differential disable */
+#ifdef CONFIG_SYS_DDR_MODE_WEAK
+			 | (1 << (16 + 1))		/* weak driver (~60%) */
+#endif
 			 | (add_lat << (16 + 3))        /* Additive Latency in EMRS1 */
 			 | (mode_odt_enable << 16)      /* ODT Enable in EMRS1 */
 			 | ((twr_clk - 1) << 9)         /* Write Recovery Autopre */