[1/2] cpu: Use STOP1 on POWER9 for idle/sleep inside OPAL

Message ID 20180511090659.13305-1-benh@kernel.crashing.org
State Accepted
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Series
  • [1/2] cpu: Use STOP1 on POWER9 for idle/sleep inside OPAL
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Commit Message

Benjamin Herrenschmidt May 11, 2018, 9:06 a.m.
The current code requests STOP3, which means it gets STOP2 in practice.

STOP2 has proven to occasionally be unreliable depending on FW
version and chip revision, it also requires a functional CME,
so instead, let's use STOP1. The difference is rather minimum
for something that is only used a few seconds during boot.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
 core/cpu.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

Stewart Smith May 25, 2018, 12:16 a.m. | #1
Benjamin Herrenschmidt <benh@kernel.crashing.org> writes:
> The current code requests STOP3, which means it gets STOP2 in practice.
>
> STOP2 has proven to occasionally be unreliable depending on FW
> version and chip revision, it also requires a functional CME,
> so instead, let's use STOP1. The difference is rather minimum
> for something that is only used a few seconds during boot.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
>  core/cpu.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)

Series merged to master as of 53dac89cb8aab986e08ea5e062564f3da9f4831f

Patch

diff --git a/core/cpu.c b/core/cpu.c
index 3e5e5922..a603e11f 100644
--- a/core/cpu.c
+++ b/core/cpu.c
@@ -409,14 +409,14 @@  static void cpu_idle_p9(enum cpu_wake_cause wake_on)
 
 	if (sreset_enabled) {
 		/* stop with EC=1 (sreset) and ESL=1 (enable thread switch). */
-		/* PSSCR SD=0 ESL=1 EC=1 PSSL=0 TR=3 MTL=0 RL=3 */
+		/* PSSCR SD=0 ESL=1 EC=1 PSSL=0 TR=3 MTL=0 RL=1 */
 		psscr = PPC_BIT(42) | PPC_BIT(43) |
-			PPC_BITMASK(54, 55) | PPC_BITMASK(62,63);
+			PPC_BITMASK(54, 55) | PPC_BIT(63);
 		enter_p9_pm_state(psscr);
 	} else {
 		/* stop with EC=0 (resumes) which does not require sreset. */
-		/* PSSCR SD=0 ESL=0 EC=0 PSSL=0 TR=3 MTL=0 RL=3 */
-		psscr = PPC_BITMASK(54, 55) | PPC_BITMASK(62,63);
+		/* PSSCR SD=0 ESL=0 EC=0 PSSL=0 TR=3 MTL=0 RL=1 */
+		psscr = PPC_BITMASK(54, 55) | PPC_BIT(63);
 		enter_p9_pm_lite_state(psscr);
 	}