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[3/9] target/ppc: Honor CPU_DUMP_FPU

Message ID 20180511035240.4016-4-richard.henderson@linaro.org
State New
Headers show
Series Honor CPU_DUMP_FPU | expand

Commit Message

Richard Henderson May 11, 2018, 3:52 a.m. UTC 
Cc: Alexander Graf <agraf@suse.de>
Cc: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/ppc/translate.c | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

Comments

Philippe Mathieu-Daudé May 13, 2018, 12:50 a.m. UTC | #1 
On 05/11/2018 12:52 AM, Richard Henderson wrote:
> Cc: Alexander Graf <agraf@suse.de>
> Cc: David Gibson <david@gibson.dropbear.id.au>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>  target/ppc/translate.c | 20 +++++++++++++-------
>  1 file changed, 13 insertions(+), 7 deletions(-)
> 
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 2a4140f420..fd66c80cc7 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -7048,14 +7048,20 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
>      }
>      cpu_fprintf(f, " ]             RES " TARGET_FMT_lx "\n",
>                  env->reserve_addr);
> -    for (i = 0; i < 32; i++) {
> -        if ((i & (RFPL - 1)) == 0)
> -            cpu_fprintf(f, "FPR%02d", i);
> -        cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
> -        if ((i & (RFPL - 1)) == (RFPL - 1))
> -            cpu_fprintf(f, "\n");
> +
> +    if (flags & CPU_DUMP_FPU) {
> +        for (i = 0; i < 32; i++) {
> +            if ((i & (RFPL - 1)) == 0) {
> +                cpu_fprintf(f, "FPR%02d", i);
> +            }
> +            cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
> +            if ((i & (RFPL - 1)) == (RFPL - 1)) {
> +                cpu_fprintf(f, "\n");
> +            }
> +        }
> +        cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
>      }
> -    cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
> +
>  #if !defined(CONFIG_USER_ONLY)
>      cpu_fprintf(f, " SRR0 " TARGET_FMT_lx "  SRR1 " TARGET_FMT_lx
>                     "    PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
>
diff mbox series

Patch

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 2a4140f420..fd66c80cc7 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7048,14 +7048,20 @@  void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
     }
     cpu_fprintf(f, " ]             RES " TARGET_FMT_lx "\n",
                 env->reserve_addr);
-    for (i = 0; i < 32; i++) {
-        if ((i & (RFPL - 1)) == 0)
-            cpu_fprintf(f, "FPR%02d", i);
-        cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
-        if ((i & (RFPL - 1)) == (RFPL - 1))
-            cpu_fprintf(f, "\n");
+
+    if (flags & CPU_DUMP_FPU) {
+        for (i = 0; i < 32; i++) {
+            if ((i & (RFPL - 1)) == 0) {
+                cpu_fprintf(f, "FPR%02d", i);
+            }
+            cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
+            if ((i & (RFPL - 1)) == (RFPL - 1)) {
+                cpu_fprintf(f, "\n");
+            }
+        }
+        cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
     }
-    cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
+
 #if !defined(CONFIG_USER_ONLY)
     cpu_fprintf(f, " SRR0 " TARGET_FMT_lx "  SRR1 " TARGET_FMT_lx
                    "    PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",