| Message ID | 1525858559-130220-1-git-send-email-mine260309@gmail.com |
|---|---|
| State | Accepted, archived |
| Headers | show |
| Series | [linux,dev-4.13,1/2] clk: aspeed: Add 24MHz fixed clock | expand |
On 9 May 2018 at 19:05, Lei YU <mine260309@gmail.com> wrote: > Add a 24MHz fixed clock. > This clock will be used for certain devices, e.g. pwm. > > Signed-off-by: Lei YU <mine260309@gmail.com> > --- > drivers/clk/clk-aspeed.c | 8 +++++++- > include/dt-bindings/clock/aspeed-clock.h | 1 + > 2 files changed, 8 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c > index c5d2af2..2ea1ec1 100644 > --- a/drivers/clk/clk-aspeed.c > +++ b/drivers/clk/clk-aspeed.c > @@ -23,7 +23,7 @@ > > #include <dt-bindings/clock/aspeed-clock.h> > > -#define ASPEED_NUM_CLKS 35 > +#define ASPEED_NUM_CLKS 36 > > #define ASPEED_RESET2_OFFSET 32 > > @@ -517,6 +517,12 @@ static int aspeed_clk_probe(struct platform_device *pdev) > return PTR_ERR(hw); > aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; > > + /* Fixed 24MHz clock */ > + hw = clk_hw_register_fixed_rate(NULL, "fixed-24m", NULL, 0, 24000000); Ryan had this to say: > it comes from external osc is soc input clock source. So we should set the parent to be "clkin". Please add that and send upstream. I'll have this with the fix to dev-4.13. Cheers, Joel > + if (IS_ERR(hw)) > + return PTR_ERR(hw); > + aspeed_clk_data->hws[ASPEED_CLK_24M] = hw; > + > /* > * TODO: There are a number of clocks that not included in this driver > * as more information is required: > diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h > index e983d17..9733c77 100644 > --- a/include/dt-bindings/clock/aspeed-clock.h > +++ b/include/dt-bindings/clock/aspeed-clock.h > @@ -37,6 +37,7 @@ > #define ASPEED_CLK_MAC 32 > #define ASPEED_CLK_BCLK 33 > #define ASPEED_CLK_MPLL 34 > +#define ASPEED_CLK_24M 35 > > #define ASPEED_RESET_XDMA 0 > #define ASPEED_RESET_MCTP 1 > -- > 2.7.4 >
diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index c5d2af2..2ea1ec1 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -23,7 +23,7 @@ #include <dt-bindings/clock/aspeed-clock.h> -#define ASPEED_NUM_CLKS 35 +#define ASPEED_NUM_CLKS 36 #define ASPEED_RESET2_OFFSET 32 @@ -517,6 +517,12 @@ static int aspeed_clk_probe(struct platform_device *pdev) return PTR_ERR(hw); aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; + /* Fixed 24MHz clock */ + hw = clk_hw_register_fixed_rate(NULL, "fixed-24m", NULL, 0, 24000000); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_24M] = hw; + /* * TODO: There are a number of clocks that not included in this driver * as more information is required: diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index e983d17..9733c77 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -37,6 +37,7 @@ #define ASPEED_CLK_MAC 32 #define ASPEED_CLK_BCLK 33 #define ASPEED_CLK_MPLL 34 +#define ASPEED_CLK_24M 35 #define ASPEED_RESET_XDMA 0 #define ASPEED_RESET_MCTP 1
Add a 24MHz fixed clock. This clock will be used for certain devices, e.g. pwm. Signed-off-by: Lei YU <mine260309@gmail.com> --- drivers/clk/clk-aspeed.c | 8 +++++++- include/dt-bindings/clock/aspeed-clock.h | 1 + 2 files changed, 8 insertions(+), 1 deletion(-)