From patchwork Tue May 8 22:49:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gilhooley X-Patchwork-Id: 910540 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40gZRy5Rn3z9s3D for ; Wed, 9 May 2018 08:49:34 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932887AbeEHWte (ORCPT ); Tue, 8 May 2018 18:49:34 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:5061 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932133AbeEHWtd (ORCPT ); Tue, 8 May 2018 18:49:33 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Tue, 08 May 2018 15:49:41 -0700 Received: from HQMAIL105.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 08 May 2018 15:49:33 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 08 May 2018 15:49:33 -0700 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 8 May 2018 22:49:33 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 8 May 2018 22:49:32 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1347.2 via Frontend Transport; Tue, 8 May 2018 22:49:32 +0000 Received: from gilhooley-newcomp.nvidia.com (Not Verified[172.17.175.31]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 08 May 2018 15:49:32 -0700 From: David Gilhooley To: , CC: , David Gilhooley Subject: [PATCH V2 2/2] arm64: capabilities: Add Nvidia Denver CPU to bp_harden list Date: Tue, 8 May 2018 15:49:43 -0700 Message-ID: <1525819783-13982-2-git-send-email-dgilhooley@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1525819783-13982-1-git-send-email-dgilhooley@nvidia.com> References: <1525819783-13982-1-git-send-email-dgilhooley@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The Nvidia Denver CPU also needs a psci call to harden the branch predictor. Signed-off-by: David Gilhooley --- arch/arm64/kernel/cpu_errata.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index a900bef..e4a1182 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -316,6 +316,7 @@ static const struct midr_range arm64_bp_harden_smccc_cpus[] = { MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1), MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR), + MIDR_ALL_VERSIONS(MIDR_NVIDIA_DENVER), {}, };