From patchwork Tue May 8 16:49:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 910343 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="SuTMN/wx"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40gQTB2yrzz9ryk for ; Wed, 9 May 2018 02:50:06 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932962AbeEHQuF (ORCPT ); Tue, 8 May 2018 12:50:05 -0400 Received: from mail-pl0-f66.google.com ([209.85.160.66]:34933 "EHLO mail-pl0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932606AbeEHQuD (ORCPT ); Tue, 8 May 2018 12:50:03 -0400 Received: by mail-pl0-f66.google.com with SMTP id i5-v6so2566881plt.2 for ; Tue, 08 May 2018 09:50:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wdFDwW2q+0Jxxc2spLGUUi8Db/0CBsx+kUYAQJ9zejE=; b=SuTMN/wxXh2AWzEcOm1WVxuDprzrLS8E5ilhwmcWTefMuKqSNBdxHQMNvV6EbdVIwe a5muBUI+Jy9oG8aWFI3PUUYvWPJOIX8ZQ/Gcsubqw+CkSoWcWdaRKCfUDrIK+D0CMVUK 4e069rNfpPV4Onsz4DNpGQkZEBrf2Y5cnsW59GIWNBJvOBJnXKm4ZsV0/EzC+7o8oxUW 6AD7X4g5nYFl4ytE3nRE6xbsgeHG7tHOJYbB47yFR9/wct7cp2d4wGCrOI2GlnFsU80X psdBAWeOCEhuncy58YQF7mgQeMyurUjjAXAJHlqae+pOfHhq31V/clA+XuK9WjGJc4Rn sDKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wdFDwW2q+0Jxxc2spLGUUi8Db/0CBsx+kUYAQJ9zejE=; b=LzIC3XNFXLSF/ONeHn18UUqrWJOkoJBrjVo1uoPi+JuNAdEZWIJ5O1AaMDhR/3MtbJ nBbzYcaDBsGHssQYuFs6sdaWELHFzLmKLUBCkm7QGaJ97K4v2wtQLBRFhu8C5RHFxnDX WUAkiKFVJhnVhlhJxb6Nn6hIFaDfWV2Vf4SrJGMXdG2Ae3zEG1O2jNf+u5384KpTEaCU Zdg6vUUpB5sHjlsJbenDlFn7lFvGObrgkJBGoJkUJBb8pMjGT9HQRXkHfxgGmadmpegU xP7+4Co8pUuZZkVujd97buBkRbOOOHlAIKtTYXjJaHeiKeSPEeYpzI40SSi0UaOZMbz9 GH7A== X-Gm-Message-State: ALQs6tCxQRNlAcJR+7eJpRsy8CA2o9t/Ay9AjBuRPLKXY1zisrAwT8Lb zlkH2S9yThBtE9q8fqauMOo= X-Google-Smtp-Source: AB8JxZpJ2qyaYDzIoDi0+2pSu5G3yNiCqlmuRyooVk6mSrHC/t33jYBT83zfjBl3NrXEWJSh71DosQ== X-Received: by 2002:a17:902:bf45:: with SMTP id u5-v6mr9842448pls.149.1525798203357; Tue, 08 May 2018 09:50:03 -0700 (PDT) Received: from localhost.localdomain ([109.252.91.130]) by smtp.gmail.com with ESMTPSA id p11-v6sm32327122pgn.18.2018.05.08.09.50.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 May 2018 09:50:02 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding Cc: linux-tegra@vger.kernel.org Subject: [PATCH 1/2] dt-bindings: memory: tegra: Remove Tegra114 SATA and AFI reset definitions Date: Tue, 8 May 2018 19:49:46 +0300 Message-Id: <20180508164947.10936-2-digetx@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180508164947.10936-1-digetx@gmail.com> References: <20180508164947.10936-1-digetx@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra114 doesn't have SATA nor PCIe, but TRM seems erroneously document them. Signed-off-by: Dmitry Osipenko --- include/dt-bindings/memory/tegra114-mc.h | 34 +++++++++++------------- 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/include/dt-bindings/memory/tegra114-mc.h b/include/dt-bindings/memory/tegra114-mc.h index 54a12adec7b8..dfe99c8a5ba5 100644 --- a/include/dt-bindings/memory/tegra114-mc.h +++ b/include/dt-bindings/memory/tegra114-mc.h @@ -23,23 +23,21 @@ #define TEGRA_SWGROUP_EMUCIF 18 #define TEGRA_SWGROUP_TSEC 19 -#define TEGRA114_MC_RESET_AFI 0 -#define TEGRA114_MC_RESET_AVPC 1 -#define TEGRA114_MC_RESET_DC 2 -#define TEGRA114_MC_RESET_DCB 3 -#define TEGRA114_MC_RESET_EPP 4 -#define TEGRA114_MC_RESET_2D 5 -#define TEGRA114_MC_RESET_HC 6 -#define TEGRA114_MC_RESET_HDA 7 -#define TEGRA114_MC_RESET_ISP 8 -#define TEGRA114_MC_RESET_MPCORE 9 -#define TEGRA114_MC_RESET_MPCORELP 10 -#define TEGRA114_MC_RESET_MPE 11 -#define TEGRA114_MC_RESET_3D 12 -#define TEGRA114_MC_RESET_3D2 13 -#define TEGRA114_MC_RESET_PPCS 14 -#define TEGRA114_MC_RESET_SATA 15 -#define TEGRA114_MC_RESET_VDE 16 -#define TEGRA114_MC_RESET_VI 17 +#define TEGRA114_MC_RESET_AVPC 0 +#define TEGRA114_MC_RESET_DC 1 +#define TEGRA114_MC_RESET_DCB 2 +#define TEGRA114_MC_RESET_EPP 3 +#define TEGRA114_MC_RESET_2D 4 +#define TEGRA114_MC_RESET_HC 5 +#define TEGRA114_MC_RESET_HDA 6 +#define TEGRA114_MC_RESET_ISP 7 +#define TEGRA114_MC_RESET_MPCORE 8 +#define TEGRA114_MC_RESET_MPCORELP 9 +#define TEGRA114_MC_RESET_MPE 10 +#define TEGRA114_MC_RESET_3D 11 +#define TEGRA114_MC_RESET_3D2 12 +#define TEGRA114_MC_RESET_PPCS 13 +#define TEGRA114_MC_RESET_VDE 14 +#define TEGRA114_MC_RESET_VI 15 #endif