Patchwork [U-Boot,V1,1/1] MX5: Keep L2 cache enabled before jump to kernel

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Submitter Jason Liu
Date April 13, 2011, 1:25 p.m.
Message ID <1302701143-10624-1-git-send-email-jason.hui@linaro.org>
Download mbox | patch
Permalink /patch/91008/
State Rejected
Headers show

Comments

Jason Liu - April 13, 2011, 1:25 p.m.
Currently, Linux kernel does not do any L2 cache enable
Operation.So,Keep L2 cache enabled(L2EN=1) in the u-boot
before Jump to the Linux Kernel and thus L2 cache can be
effectively used in Linux Kernel.

Signed-off-by: Jason Liu <jason.hui@linaro.org>
---
 arch/arm/cpu/armv7/mx5/Makefile           |    2 +-
 arch/arm/cpu/armv7/mx5/cache.S            |   43 +++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/mx5/soc.c              |    6 ++++
 arch/arm/include/asm/arch-mx5/sys_proto.h |    2 +
 include/configs/mx51evk.h                 |    2 -
 include/configs/mx53evk.h                 |    2 -
 include/configs/mx53loco.h                |    2 -
 7 files changed, 52 insertions(+), 7 deletions(-)
Albert ARIBAUD - April 14, 2011, 12:09 p.m.
Hi Jason,

Le 13/04/2011 15:25, Jason Liu a écrit :
> Currently, Linux kernel does not do any L2 cache enable
> Operation.So,Keep L2 cache enabled(L2EN=1) in the u-boot
> before Jump to the Linux Kernel and thus L2 cache can be
> effectively used in Linux Kernel.

Do you mean that the Linux Kernel has L2 cache support except for 
enabling it? It would seem to me the most logical thing would be to 
enable the cache in Linux then, rather than expecting the bootloader to 
do it.

Amicalement,
Stefano Babic - April 15, 2011, 3:09 p.m.
On 04/13/2011 03:25 PM, Jason Liu wrote:

Hi Jason,

> Currently, Linux kernel does not do any L2 cache enable
> Operation.So,Keep L2 cache enabled(L2EN=1) in the u-boot
> before Jump to the Linux Kernel and thus L2 cache can be
> effectively used in Linux Kernel.

If the cache is not active in the kernel for MX5, this should be fixed
in the kernel for this architecture. Normally, cache is activated inside
the kernel itself, as I cann see for other architectures and other ARMV7
processors (omap)

However, if you plan to add cache support, why not add the functions to
get the cache enabled in u-boot ?

> +
> +/*
> + * Sine we did not enable D-cache in uboot,this is the
> + * Dummy function for L2 ON to make build pass. please
> + * Check the arch/arm/cpu/armv7/cpu.c file
> + */

This seems to me a workaround for a non clear problem (at least, not
clear for me..) to activate the cache at the startup of the kernel.
There are already processors in u-boot supporting the cache, and if we
add caching functions to u-boot for i.MX5, we must implement the full
support to have cache active in the bootloader.


> +invalidate_dcache:
> +	mov	pc, lr
> +
> +l2_cache_enable:
> +	mrc	p15, 0, r0, c1, c0, 1;

No registers are saved before calling this funtion ?

Best regards,
Stefano Babic
Jason Liu - April 15, 2011, 3:55 p.m.
Hi, Stefano,

2011/4/15 Stefano Babic <sbabic@denx.de>:
> On 04/13/2011 03:25 PM, Jason Liu wrote:
>
> Hi Jason,
>
>> Currently, Linux kernel does not do any L2 cache enable
>> Operation.So,Keep L2 cache enabled(L2EN=1) in the u-boot
>> before Jump to the Linux Kernel and thus L2 cache can be
>> effectively used in Linux Kernel.
>
> If the cache is not active in the kernel for MX5, this should be fixed
> in the kernel for this architecture. Normally, cache is activated inside
> the kernel itself, as I cann see for other architectures and other ARMV7
> processors (omap)

Here the cache is L2 cache. I have observed that if uboot does not enable it,
then L2 cache will not get enabled through current ARM linux core code.

And for the uboot itself it provide the following code in cpu.c to
enable L2 cache
before jump to linux kernel, and this code maybe implemented by omap guys:
If linux kernel already enabled it, then there is no need for the L2
related code here?

int cleanup_before_linux(void)
{
        unsigned int i;

        /*
         * this function is called just before we call linux
         * it prepares the processor for linux
         *
         * we turn off caches etc ...
         */
        disable_interrupts();

        /* turn off I/D-cache */
        icache_disable();
        dcache_disable();

        /* invalidate I-cache */
        cache_flush();

#ifndef CONFIG_L2_OFF
        /* turn off L2 cache */
        l2_cache_disable();
        /* invalidate L2 cache also */
        invalidate_dcache(get_device_type());
#endif
        i = 0;
        /* mem barrier to sync up things */
        asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));

#ifndef CONFIG_L2_OFF
        l2_cache_enable();
#endif

>
> However, if you plan to add cache support, why not add the functions to
> get the cache enabled in u-boot ?

Yes, good point.
This is my to-do task but It will need much work to make the driver work
when enable d-cache support.

>
>> +
>> +/*
>> + * Sine we did not enable D-cache in uboot,this is the
>> + * Dummy function for L2 ON to make build pass. please
>> + * Check the arch/arm/cpu/armv7/cpu.c file
>> + */
>
> This seems to me a workaround for a non clear problem (at least, not
> clear for me..) to activate the cache at the startup of the kernel.
> There are already processors in u-boot supporting the cache, and if we
> add caching functions to u-boot for i.MX5, we must implement the full
> support to have cache active in the bootloader.

Here, as the comment said, since uboot does not enable L2 cache before
it jump to linux kernel, so, this function is just the dummy function to
pass build. Take the code from arch/arm/cpu/armv7/cpu.c:
int cleanup_before_linux(void)
{
...
#ifndef CONFIG_L2_OFF
        /* turn off L2 cache */
        l2_cache_disable();
        /* invalidate L2 cache also */
        invalidate_dcache(get_device_type());
#endif

>
>
>> +invalidate_dcache:
>> +     mov     pc, lr
>> +
>> +l2_cache_enable:
>> +     mrc     p15, 0, r0, c1, c0, 1;
>
> No registers are saved before calling this funtion ?

I don't think it needs save any register.

Jason

>
> Best regards,
> Stefano Babic
>
> --
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>
Albert ARIBAUD - April 16, 2011, 9:55 a.m.
Le 15/04/2011 17:55, Jason Liu a écrit :
> Hi, Stefano,
>
> 2011/4/15 Stefano Babic<sbabic@denx.de>:
>> On 04/13/2011 03:25 PM, Jason Liu wrote:
>>
>> Hi Jason,
>>
>>> Currently, Linux kernel does not do any L2 cache enable
>>> Operation.So,Keep L2 cache enabled(L2EN=1) in the u-boot
>>> before Jump to the Linux Kernel and thus L2 cache can be
>>> effectively used in Linux Kernel.
>>
>> If the cache is not active in the kernel for MX5, this should be fixed
>> in the kernel for this architecture. Normally, cache is activated inside
>> the kernel itself, as I cann see for other architectures and other ARMV7
>> processors (omap)
>
> Here the cache is L2 cache. I have observed that if uboot does not enable it,
> then L2 cache will not get enabled through current ARM linux core code.

Which still does not tell us why Linux should depend on some bootloader 
for enabling L2 cache. If Linux does not enable L2 cache, there is a 
reason and we should not enable the L2 cache in Linux' back; 
conversively, if Linux wants L2 cache enabled, then let Linux do it.

> And for the uboot itself it provide the following code in cpu.c to
> enable L2 cache
> before jump to linux kernel, and this code maybe implemented by omap guys:
> If linux kernel already enabled it, then there is no need for the L2
> related code here?

Turning caches OFF before jumping to Linux is a sane thing to do. 
Re-enabling it, on the other hand, bears no reason that I can discern, 
because Linux can do it just as well, and it is better if Linux does it 
because it will do it exactly where and when it is ready for it, and 
because this removes a dependency between Linux and the bootloader, 
which is a Good Thing (tm).

Amicalement,

Patch

diff --git a/arch/arm/cpu/armv7/mx5/Makefile b/arch/arm/cpu/armv7/mx5/Makefile
index e8be9c9..a7df7a6 100644
--- a/arch/arm/cpu/armv7/mx5/Makefile
+++ b/arch/arm/cpu/armv7/mx5/Makefile
@@ -28,7 +28,7 @@  include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(SOC).o
 
 COBJS	= soc.o clock.o iomux.o timer.o speed.o
-SOBJS = lowlevel_init.o
+SOBJS = lowlevel_init.o cache.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/arch/arm/cpu/armv7/mx5/cache.S b/arch/arm/cpu/armv7/mx5/cache.S
new file mode 100644
index 0000000..c81c8be
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx5/cache.S
@@ -0,0 +1,43 @@ 
+/*
+ * Copyright 2011 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+.align 5
+.global invalidate_dcache
+.global l2_cache_enable
+.global l2_cache_disable
+
+/*
+ * Sine we did not enable D-cache in uboot,this is the
+ * Dummy function for L2 ON to make build pass. please
+ * Check the arch/arm/cpu/armv7/cpu.c file
+ */
+invalidate_dcache:
+	mov	pc, lr
+
+l2_cache_enable:
+	mrc	p15, 0, r0, c1, c0, 1;
+	orr	r0, r0, #0x2
+	mcr	p15, 0, r0, c1, c0, 1;
+	mov	pc, lr
+
+l2_cache_disable:
+	mrc	p15, 0, r0, c1, c0, 1;
+	bic	r0, r0, #0x2
+	mcr	p15, 0, r0, c1, c0, 1;
+	mov	pc, lr
diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c
index 09500b3..e3b6269 100644
--- a/arch/arm/cpu/armv7/mx5/soc.c
+++ b/arch/arm/cpu/armv7/mx5/soc.c
@@ -144,3 +144,9 @@  void reset_cpu(ulong addr)
 {
 	__raw_writew(4, WDOG1_BASE_ADDR);
 }
+
+/*dummy function for L2 ON*/
+u32 get_device_type(void)
+{
+	return 0;
+}
diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h
index f687503..89ab8e8 100644
--- a/arch/arm/include/asm/arch-mx5/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx5/sys_proto.h
@@ -27,5 +27,7 @@ 
 u32 get_cpu_rev(void);
 #define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
 void sdelay(unsigned long);
+void invalidate_dcache(u32);
+u32 get_device_type(void);
 
 #endif
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 50caacd..abf6cb9 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -35,8 +35,6 @@ 
 
 #define CONFIG_SYS_TEXT_BASE	0x97800000
 
-#define CONFIG_L2_OFF
-
 #include <asm/arch/imx-regs.h>
 /*
  * Disabled for now due to build problems under Debian and a significant
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
index 6ac910b..410795f 100644
--- a/include/configs/mx53evk.h
+++ b/include/configs/mx53evk.h
@@ -29,8 +29,6 @@ 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
-#define CONFIG_L2_OFF
-
 #include <asm/arch/imx-regs.h>
 
 #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 9c7dcc9..1e60335 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -30,8 +30,6 @@ 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
-#define CONFIG_L2_OFF
-
 #include <asm/arch/imx-regs.h>
 
 #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */