From patchwork Fri May 4 10:28:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 908655 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40cpFl6DJYz9s1d for ; Fri, 4 May 2018 20:31:07 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 40cpFl4rC1zDr4q for ; Fri, 4 May 2018 20:31:07 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=hegdevasant@linux.vnet.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 40cpCR0lyxzDsPd for ; Fri, 4 May 2018 20:29:06 +1000 (AEST) Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w44AT2di059711 for ; Fri, 4 May 2018 06:29:04 -0400 Received: from e06smtp10.uk.ibm.com (e06smtp10.uk.ibm.com [195.75.94.106]) by mx0b-001b2d01.pphosted.com with ESMTP id 2hrmvrjr14-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 04 May 2018 06:29:03 -0400 Received: from localhost by e06smtp10.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 4 May 2018 11:28:59 +0100 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w44ASxhw41156856; Fri, 4 May 2018 10:28:59 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AA79911C05C; Fri, 4 May 2018 11:20:31 +0100 (BST) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 59C3811C050; Fri, 4 May 2018 11:20:30 +0100 (BST) Received: from hegdevasant.in.ibm.com (unknown [9.199.177.123]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 4 May 2018 11:20:30 +0100 (BST) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 4 May 2018 15:58:12 +0530 X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180504102817.11059-1-hegdevasant@linux.vnet.ibm.com> References: <20180504102817.11059-1-hegdevasant@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18050410-0040-0000-0000-00000435F073 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18050410-0041-0000-0000-0000263A18A8 Message-Id: <20180504102817.11059-13-hegdevasant@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-05-04_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1805040097 Subject: [Skiboot] [PATCH v2 12/17] hdata: Add architected register support X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stewart@linux.vnet.ibm.com MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Post MPIPL FSP/hostboot passes architected register data via HDAT. Add support get architected register data from HDAT and pass it to kernel. Kernel will use this data to generate vmcore and opalcore. This patch moves 'proc_dump_area' ntuple from SPIRAH to SPIRAS..as HDAT provides 'proc_dump_area' under SPIRAS. Device tree properties under /ibm,dump node: cpu-data-version - Architected register data format version cpu-data-size - Each CPU register data size result-table - Add entry for architected register Based on cpu-data-size and result-table, kernel will be able to get data for indivisual CPU/register. Signed-off-by: Vasant Hegde --- hdata/spira.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++-- hdata/spira.h | 20 +++++++++++++++----- 2 files changed, 65 insertions(+), 7 deletions(-) diff --git a/hdata/spira.c b/hdata/spira.c index 00bfa87a5..aa2733762 100644 --- a/hdata/spira.c +++ b/hdata/spira.c @@ -1121,6 +1121,47 @@ static void add_iplparams_sys_params(const void *iplp, struct dt_node *node) dt_init_secureboot_node(p); } +/* Map architected register data from HDAT memory to result-table */ +static int fadump_add_arch_regs(struct dt_node *node, + struct fadump *result_table, int *res_cnt) +{ + u64 size, *addr; + const struct HDIF_common_hdr *reg_hdif; + const struct HDIF_array_hdr *reg_data; + struct fadump_section *fadump_section; + + reg_hdif = get_hdif(&spira.ntuples.proc_dump_area, PROC_DUMP_HDIF_SIG); + if (!reg_hdif) { + prlog(PR_ERR, "FADUMP: Architected register is missing\n"); + return OPAL_HARDWARE; + } + + reg_data = HDIF_get_idata(reg_hdif, PROC_DUMP_ARCH_REG_DATA, NULL); + if (!CHECK_SPPTR(reg_data)) { + prlog(PR_ERR, "FADUMP: Invalid architected register data\n"); + return OPAL_HARDWARE; + } + + /* Add each thread size */ + dt_add_property_cells(node, "cpu-data-size", + be32_to_cpu(reg_data->eactsz)); + prlog(PR_TRACE, "FADUMP: Architected regs : thread count = %x, " + "size of each thread = %x\n", + be32_to_cpu(reg_data->ecnt), be32_to_cpu(reg_data->eactsz)); + + size = be32_to_cpu(reg_data->ecnt) * be32_to_cpu(reg_data->eactsz); + addr = (void *)reg_data + be32_to_cpu(reg_data->offset); + + fadump_section = &(result_table->section[*res_cnt]); + fadump_section->source_type = DUMP_REGION_CPU_DATA; + fadump_section->source_addr = (u64)addr; + fadump_section->dest_addr = (u64)addr; + fadump_section->source_size = size; + fadump_section->dest_size = size; + (*res_cnt)++; + return OPAL_SUCCESS; +} + static void fadump_add_result_table(struct dt_node *node, const struct iplparams_iplparams *p) { @@ -1148,9 +1189,9 @@ static void fadump_add_result_table(struct dt_node *node, prlog(PR_DEBUG, "FADUMP: Dump found, MDRT count = 0x%x\n", mdrt_cnt); - /* Number of entries in MDRT table */ + /* Number of entries in MDRT table + 1 for arch register data */ prop_size = sizeof(struct fadump) + - (mdrt_cnt * sizeof(struct fadump_section)); + ((mdrt_cnt + 1) * sizeof(struct fadump_section)); result_table = zalloc(prop_size); if (!result_table) { prlog(PR_ERR, "FADUMP: Failed to allocate memory\n"); @@ -1187,6 +1228,9 @@ static void fadump_add_result_table(struct dt_node *node, return; } + /* Add architected register data to result-table */ + fadump_add_arch_regs(node, result_table, &j); + result_table->section_count = j; /* Actual property size */ prop_size = sizeof(struct fadump) + (j * sizeof(struct fadump_section)); @@ -1212,6 +1256,9 @@ static void fadump_add_node(const struct iplparams_iplparams *p) fw_load_area[3] = INITRAMFS_LOAD_SIZE; dt_add_property(node, "fw-load-area", fw_load_area, sizeof(fw_load_area)); + /* Architected register data format version */ + dt_add_property_cells(node, "cpu-data-version", PROC_DUMP_ARCH_REG_VER); + fadump_add_result_table(node, p); } @@ -1801,6 +1848,7 @@ static void fixup_spira(void) spira.ntuples.hs_data = spiras->ntuples.hs_data; spira.ntuples.ipmi_sensor = spiras->ntuples.ipmi_sensor; spira.ntuples.node_stb_data = spiras->ntuples.node_stb_data; + spira.ntuples.proc_dump_area = spiras->ntuples.proc_dump_area; } /* diff --git a/hdata/spira.h b/hdata/spira.h index 46d7c70c8..e0766fd49 100644 --- a/hdata/spira.h +++ b/hdata/spira.h @@ -76,6 +76,7 @@ struct spira_ntuples { struct spira_ntuple hs_data; /* 0x320 */ struct spira_ntuple ipmi_sensor; /* 0x360 */ struct spira_ntuple node_stb_data; /* 0x380 */ + struct spira_ntuple proc_dump_area; /* 0x3a0 */ }; struct spira { @@ -89,7 +90,7 @@ struct spira { * * According to FSP engineers, this is an okay thing to do. */ - u8 reserved[0x80]; + u8 reserved[0x40]; } __packed __align(0x100); extern struct spira spira; @@ -111,7 +112,6 @@ struct spirah_ntuples { struct spira_ntuple mdump_src; /* 0x0a0 */ struct spira_ntuple mdump_dst; /* 0x0c0 */ struct spira_ntuple mdump_res; /* 0x0e0 */ - struct spira_ntuple proc_dump_area; /* 0x100 */ }; struct spirah { @@ -119,7 +119,7 @@ struct spirah { struct HDIF_idata_ptr ntuples_ptr; __be64 pad; struct spirah_ntuples ntuples; - u8 reserved[0xE0]; + u8 reserved[0x100]; } __packed __align(0x100); extern struct spirah spirah; @@ -132,7 +132,7 @@ extern struct spirah spirah; #define SPIRAS_VERSION_P9 0x50 /* N-tuples in SPIRAS */ -#define SPIRAS_NTUPLES_COUNT 0x10 +#define SPIRAS_NTUPLES_COUNT 0x13 struct spiras_ntuples { struct HDIF_array_hdr array_hdr; /* 0x030 */ @@ -154,6 +154,7 @@ struct spiras_ntuples { struct spira_ntuple hbrt_data; /* 0x220 */ struct spira_ntuple ipmi_sensor; /* 0x240 */ struct spira_ntuple node_stb_data; /* 0x260 */ + struct spira_ntuple proc_dump_area; /* 0x280 */ }; struct spiras { @@ -161,7 +162,7 @@ struct spiras { struct HDIF_idata_ptr ntuples_ptr; __be64 pad; struct spiras_ntuples ntuples; - u8 reserved[0x180]; + u8 reserved[0x160]; } __packed __align(0x100); extern struct spiras *spiras; @@ -1291,6 +1292,15 @@ struct hash_and_verification { __be32 offset; } __packed; + +/* Processor dump area. Used by MPIPL boot to get architected register data */ +#define PROC_DUMP_HDIF_SIG "ARCREG" + +/* Idata index 0 : Architected register data area */ +#define PROC_DUMP_ARCH_REG_DATA 0 + +#define PROC_DUMP_ARCH_REG_VER 0x10 /* P9 format */ + static inline const char *cpu_state(u32 flags) { switch ((flags & CPU_ID_VERIFY_MASK) >> CPU_ID_VERIFY_SHIFT) {