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[109.252.91.130]) by smtp.gmail.com with ESMTPSA id h20-v6sm2995858ljj.85.2018.05.03.15.56.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 May 2018 15:56:16 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Stephen Boyd , Michael Turquette , Linus Walleij , Marcel Ziswiler , Marc Dietrich Cc: linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2] pinctrl: tegra20: Provide CDEV1/2 clock muxes Date: Fri, 4 May 2018 01:55:34 +0300 Message-Id: <20180503225537.20748-3-digetx@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180503225537.20748-1-digetx@gmail.com> References: <20180503225537.20748-1-digetx@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Muxing of pins MCLK1/2 determine the muxing of the corresponding clocks. Make pinctrl driver to provide clock muxes for the CDEV1/2 pingroups, so that main clk-controller driver could get an actual parent clock for the CDEV1/2 clocks. Signed-off-by: Dmitry Osipenko Reviewed-by: Marcel Ziswiler Tested-by: Marcel Ziswiler Tested-by: Marc Dietrich Acked-by: Peter De Schrijver --- v2: This patch is factored out from the v1 clk/DT series so that it could be applied separately. drivers/pinctrl/tegra/pinctrl-tegra.c | 11 --------- drivers/pinctrl/tegra/pinctrl-tegra.h | 11 +++++++++ drivers/pinctrl/tegra/pinctrl-tegra20.c | 30 ++++++++++++++++++++++++- 3 files changed, 40 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 72c718e66ebb..49c7c1499bc3 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -33,17 +33,6 @@ #include "../pinctrl-utils.h" #include "pinctrl-tegra.h" -struct tegra_pmx { - struct device *dev; - struct pinctrl_dev *pctl; - - const struct tegra_pinctrl_soc_data *soc; - const char **group_pins; - - int nbanks; - void __iomem **regs; -}; - static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg) { return readl(pmx->regs[bank] + reg); diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h index 33b17cb1471e..aa33c20766c4 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.h +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h @@ -16,6 +16,17 @@ #ifndef __PINMUX_TEGRA_H__ #define __PINMUX_TEGRA_H__ +struct tegra_pmx { + struct device *dev; + struct pinctrl_dev *pctl; + + const struct tegra_pinctrl_soc_data *soc; + const char **group_pins; + + int nbanks; + void __iomem **regs; +}; + enum tegra_pinconf_param { /* argument: tegra_pinconf_pull */ TEGRA_PINCONF_PARAM_PULL, diff --git a/drivers/pinctrl/tegra/pinctrl-tegra20.c b/drivers/pinctrl/tegra/pinctrl-tegra20.c index 7e38ee9bae78..b6dd939d32cc 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra20.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra20.c @@ -19,6 +19,7 @@ * more details. */ +#include #include #include #include @@ -2231,9 +2232,36 @@ static const struct tegra_pinctrl_soc_data tegra20_pinctrl = { .drvtype_in_mux = false, }; +static const char *cdev1_parents[] = { + "dev1_osc_div", "pll_a_out0", "pll_m_out1", "audio", +}; + +static const char *cdev2_parents[] = { + "dev2_osc_div", "hclk", "pclk", "pll_p_out4", +}; + +static void tegra20_pinctrl_register_clock_muxes(struct platform_device *pdev) +{ + struct tegra_pmx *pmx = platform_get_drvdata(pdev); + + clk_register_mux(NULL, "cdev1_mux", cdev1_parents, 4, 0, + pmx->regs[1] + 0x8, 2, 2, CLK_MUX_READ_ONLY, NULL); + + clk_register_mux(NULL, "cdev2_mux", cdev2_parents, 4, 0, + pmx->regs[1] + 0x8, 4, 2, CLK_MUX_READ_ONLY, NULL); +} + static int tegra20_pinctrl_probe(struct platform_device *pdev) { - return tegra_pinctrl_probe(pdev, &tegra20_pinctrl); + int err; + + err = tegra_pinctrl_probe(pdev, &tegra20_pinctrl); + if (err) + return err; + + tegra20_pinctrl_register_clock_muxes(pdev); + + return 0; } static const struct of_device_id tegra20_pinctrl_of_match[] = {