diff mbox series

[v1,14/29] target-microblaze: Name special registers we support

Message ID 20180503091922.28733-15-edgar.iglesias@gmail.com
State New
Headers show
Series [v1,01/29] target-microblaze: dec_load: Use bool instead of unsigned int | expand

Commit Message

Edgar E. Iglesias May 3, 2018, 9:19 a.m. UTC
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Name special registers we support.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/translate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Alistair Francis May 3, 2018, 8:30 p.m. UTC | #1
On Thu, May 3, 2018 at 2:28 AM Edgar E. Iglesias <edgar.iglesias@gmail.com>
wrote:

> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

> Name special registers we support.

> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
>   target/microblaze/translate.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)

> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index c971fe3b72..57cd00ab3e 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -105,8 +105,8 @@ static const char *regnames[] =

>   static const char *special_regnames[] =
>   {
> -    "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
> -    "sr8", "sr9", "sr10", "sr11", "sr12", "sr13"
> +    "rpc", "rmsr", "sr2", "rear", "sr4", "resr", "sr6", "rfsr",
> +    "sr8", "sr9", "sr10", "rbtr", "sr12", "rbtr"

Hey Edgar,

Where do the two rbtr registers come from?

Alistair

>   };

>   static inline void t_sync_flags(DisasContext *dc)
> --
> 2.14.1
Edgar E. Iglesias May 5, 2018, 1:30 p.m. UTC | #2
On Thu, May 03, 2018 at 08:30:13PM +0000, Alistair Francis wrote:
> On Thu, May 3, 2018 at 2:28 AM Edgar E. Iglesias <edgar.iglesias@gmail.com>
> wrote:
> 
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> 
> > Name special registers we support.
> 
> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > ---
> >   target/microblaze/translate.c | 4 ++--
> >   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> > diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> > index c971fe3b72..57cd00ab3e 100644
> > --- a/target/microblaze/translate.c
> > +++ b/target/microblaze/translate.c
> > @@ -105,8 +105,8 @@ static const char *regnames[] =
> 
> >   static const char *special_regnames[] =
> >   {
> > -    "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
> > -    "sr8", "sr9", "sr10", "sr11", "sr12", "sr13"
> > +    "rpc", "rmsr", "sr2", "rear", "sr4", "resr", "sr6", "rfsr",
> > +    "sr8", "sr9", "sr10", "rbtr", "sr12", "rbtr"
> 
> Hey Edgar,
> 
> Where do the two rbtr registers come from?

Thanks Alistair, sr13 should be redr. I've fixed it in v2.

Cheers,
Edgar
diff mbox series

Patch

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index c971fe3b72..57cd00ab3e 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -105,8 +105,8 @@  static const char *regnames[] =
 
 static const char *special_regnames[] =
 {
-    "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
-    "sr8", "sr9", "sr10", "sr11", "sr12", "sr13"
+    "rpc", "rmsr", "sr2", "rear", "sr4", "resr", "sr6", "rfsr",
+    "sr8", "sr9", "sr10", "rbtr", "sr12", "rbtr"
 };
 
 static inline void t_sync_flags(DisasContext *dc)