Patchwork [ARM] Fix PR48090

login
register
mail settings
Submitter Ramana Radhakrishnan
Date April 12, 2011, 8:05 a.m.
Message ID <4DA407D6.6@linaro.org>
Download mbox | patch
Permalink /patch/90737/
State New
Headers show

Comments

Ramana Radhakrishnan - April 12, 2011, 8:05 a.m.
Hi,

This should fix PR48090 and should be applied to all release branches. 
The first alternative doesn't need an early clobber since it is tied to 
operand 0 - the second alternative however does need one. This is a bug 
that manifests itself with a particular set of command line options and 
it is interesting to note that this hasn't been caught in such a long time.

Testing in progress . Ok to commit to all release branches ?

cheers
Ramana

2011-04-11  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>

	PR target/48090
	* config/arm/arm.md (*arm_negdi2): Fix early clobber constraints.


    "TARGET_ARM"
Richard Earnshaw - April 12, 2011, 9:31 a.m.
On Tue, 2011-04-12 at 09:05 +0100, Ramana Radhakrishnan wrote:
> Hi,
> 
> This should fix PR48090 and should be applied to all release branches. 
> The first alternative doesn't need an early clobber since it is tied to 
> operand 0 - the second alternative however does need one. This is a bug 
> that manifests itself with a particular set of command line options and 
> it is interesting to note that this hasn't been caught in such a long time.
> 
> Testing in progress . Ok to commit to all release branches ?
> 
> cheers
> Ramana
> 
> 2011-04-11  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
> 
> 	PR target/48090
> 	* config/arm/arm.md (*arm_negdi2): Fix early clobber constraints.
> 

OK everywhere.

R.

Patch

Index: gcc/config/arm/arm.md
===================================================================
--- gcc/config/arm/arm.md	(revision 172252)
+++ gcc/config/arm/arm.md	(working copy)
@@ -3554,7 +3554,7 @@ 
  ;; The constraints here are to prevent a *partial* overlap (where %Q0 
== %R1).
  ;; The first alternative allows the common case of a *full* overlap.
  (define_insn "*arm_negdi2"
-  [(set (match_operand:DI         0 "s_register_operand" "=&r,r")
+  [(set (match_operand:DI         0 "s_register_operand" "=r,&r")
  	(neg:DI (match_operand:DI 1 "s_register_operand"  "0,r")))
     (clobber (reg:CC CC_REGNUM))]