Patchwork [U-Boot] STx AMC8548: initial support for Silicon Turnkey Express AMC8548 board

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Submitter Alex Dubov
Date April 12, 2011, 5:04 a.m.
Message ID <1302584653-15312-1-git-send-email-oakad@yahoo.com>
Download mbox | patch
Permalink /patch/90713/
State Changes Requested
Delegated to: Kumar Gala
Headers show

Comments

Alex Dubov - April 12, 2011, 5:04 a.m.
From: Alex Dubov <oakad@yahoo.com>

AMC8548 is a RapidIO development board in AMC form factor, featuring MPC8548E
processor, DDR2 SO-DIMM slot, 16MB of hardwired NAND flash memory, real time
clock and additional serial EEPROM on i2c bus (enabled). USB controller is
available, but not presently enabled.

Additional board information is available at:
http://www.silicontkx.com/AMC8548.htm

Signed-off-by: Alex Dubov <oakad@yahoo.com>
---
 MAINTAINERS                       |    2 +
 board/stx/stxamc8548/Makefile     |   53 ++++++
 board/stx/stxamc8548/law.c        |   50 +++++
 board/stx/stxamc8548/stxamc8548.c |  120 ++++++++++++
 board/stx/stxamc8548/tlb.c        |   82 ++++++++
 boards.cfg                        |    1 +
 include/configs/stxamc8548.h      |  374 +++++++++++++++++++++++++++++++++++++
 7 files changed, 682 insertions(+), 0 deletions(-)
 create mode 100644 board/stx/stxamc8548/Makefile
 create mode 100644 board/stx/stxamc8548/law.c
 create mode 100644 board/stx/stxamc8548/stxamc8548.c
 create mode 100644 board/stx/stxamc8548/tlb.c
 create mode 100644 include/configs/stxamc8548.h
Wolfgang Denk - Oct. 15, 2011, 9:11 p.m.
Dear Kumar,

In message <1302584653-15312-1-git-send-email-oakad@yahoo.com> Alex
Dubov wrote:
> From: Alex Dubov <oakad@yahoo.com>
> 
> AMC8548 is a RapidIO development board in AMC form factor, featuring MPC8548E
> processor, DDR2 SO-DIMM slot, 16MB of hardwired NAND flash memory, real time
> clock and additional serial EEPROM on i2c bus (enabled). USB controller is
> available, but not presently enabled.
> 
> Additional board information is available at:
> http://www.silicontkx.com/AMC8548.htm
> 
> Signed-off-by: Alex Dubov <oakad@yahoo.com>

Can you please comment on the status of this patch?

http://article.gmane.org/gmane.comp.boot-loaders.u-boot/97396
ID    State        Name
--    -----        ----
80612 New          [U-Boot] STx AMC8548: initial support for Silicon Turnkey Express AMC8548 board
90713 New          [U-Boot] STx AMC8548: initial support for Silicon Turnkey Express AMC8548 board


Best regards,

Wolfgang Denk
Kumar Gala - Oct. 16, 2011, 3:02 p.m.
On Apr 12, 2011, at 12:04 AM, Alex Dubov wrote:

> From: Alex Dubov <oakad@yahoo.com>
> 
> AMC8548 is a RapidIO development board in AMC form factor, featuring MPC8548E
> processor, DDR2 SO-DIMM slot, 16MB of hardwired NAND flash memory, real time
> clock and additional serial EEPROM on i2c bus (enabled). USB controller is
> available, but not presently enabled.
> 
> Additional board information is available at:
> http://www.silicontkx.com/AMC8548.htm
> 
> Signed-off-by: Alex Dubov <oakad@yahoo.com>
> ---
> MAINTAINERS                       |    2 +
> board/stx/stxamc8548/Makefile     |   53 ++++++
> board/stx/stxamc8548/law.c        |   50 +++++
> board/stx/stxamc8548/stxamc8548.c |  120 ++++++++++++
> board/stx/stxamc8548/tlb.c        |   82 ++++++++
> boards.cfg                        |    1 +
> include/configs/stxamc8548.h      |  374 +++++++++++++++++++++++++++++++++++++
> 7 files changed, 682 insertions(+), 0 deletions(-)
> create mode 100644 board/stx/stxamc8548/Makefile
> create mode 100644 board/stx/stxamc8548/law.c
> create mode 100644 board/stx/stxamc8548/stxamc8548.c
> create mode 100644 board/stx/stxamc8548/tlb.c
> create mode 100644 include/configs/stxamc8548.h

Patch needs some minor updates to apply & build with current HEAD.  Please make those.

- k
Alex Dubov - Oct. 18, 2011, 9:02 a.m.
----- Original Message -----

> From: Kumar Gala <galak@kernel.crashing.org>
> 
> 
> On Apr 12, 2011, at 12:04 AM, Alex Dubov wrote:
> 
>>  From: Alex Dubov <oakad@yahoo.com>
>> 
>>  AMC8548 is a RapidIO development board in AMC form factor, featuring 
> MPC8548E
> 
> Patch needs some minor updates to apply & build with current HEAD.  Please 
> make those.

I've already told Wolgang that I will probably be unable to maintain this thing anyway.


> 
> - k
>
Kumar Gala - Oct. 18, 2011, 1:09 p.m.
On Oct 18, 2011, at 4:02 AM, Alex Dubov wrote:

> ----- Original Message -----
> 
>> From: Kumar Gala <galak@kernel.crashing.org>
>> 
>> 
>> On Apr 12, 2011, at 12:04 AM, Alex Dubov wrote:
>> 
>>> From: Alex Dubov <oakad@yahoo.com>
>>> 
>>> AMC8548 is a RapidIO development board in AMC form factor, featuring 
>> MPC8548E
>> 
>> Patch needs some minor updates to apply & build with current HEAD.  Please 
>> make those.
> 
> I've already told Wolgang that I will probably be unable to maintain this thing anyway.

Ok, will consider it dropped

- k

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index d0fc7dc..116e34c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -139,7 +139,9 @@  Jon Diekema <jon.diekema@smiths-aerospace.com>
 	sbc8260		MPC8260
 
 Alex Dubov <oakad@yahoo.com>
+
 	mpq101		MPC8548
+	stxamc8548	MPC8548
 
 Dirk Eibach <eibach@gdsys.de>
 
diff --git a/board/stx/stxamc8548/Makefile b/board/stx/stxamc8548/Makefile
new file mode 100644
index 0000000..58bc1b3
--- /dev/null
+++ b/board/stx/stxamc8548/Makefile
@@ -0,0 +1,53 @@ 
+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/stx/stxamc8548/law.c b/board/stx/stxamc8548/law.c
new file mode 100644
index 0000000..0a435d9
--- /dev/null
+++ b/board/stx/stxamc8548/law.c
@@ -0,0 +1,50 @@ 
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x1fff_ffff     DDR     (set elsewhere) autodetect
+ * 0xc000_0000     0xdfff_ffff     RapidIO (set elsewhere) 512M
+ * 0xe000_0000     0xe000_ffff     CCSR    (set elsewhere) 1M
+ * 0xf000_0000     0xffff_ffff     LBC options + FLASH     256M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * LAW 0 is reserved for boot mapping
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_LBC_OPTION_BASE_PHYS, LAW_SIZE_256M,
+		LAW_TRGT_IF_LBC)
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/stx/stxamc8548/stxamc8548.c b/board/stx/stxamc8548/stxamc8548.c
new file mode 100644
index 0000000..e0c4f9c
--- /dev/null
+++ b/board/stx/stxamc8548/stxamc8548.c
@@ -0,0 +1,120 @@ 
+/*
+ * (C) Copyright 2011 Alex Dubov <oakad@yahoo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <i2c.h>
+
+/*
+ * Initialize Local Bus
+ */
+void local_bus_init(void)
+{
+	fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
+	out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
+}
+
+int checkboard(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+
+	puts("Board: Silicon Turnkey Express AMC8548 ");
+#ifdef CONFIG_PHYS_64BIT
+	puts("(36-bit addrmap) ");
+#endif
+	putc('\n');
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init();
+
+	/*
+	 * Hack TSEC 3 and 4 IO voltages.
+	 */
+	out_be32(&gur->tsec34ioovcr, 0xe7e0); /*  1110 0111 1110 0xxx */
+
+	out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
+	out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
+	return 0;
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num)
+{
+	int rc = 0;
+
+	if (ctrl_num == 0) {
+		rc = i2c_read(SPD_EEPROM_ADDRESS, 0, 1, (uchar *)ctrl_dimms_spd,
+			      sizeof(ddr2_spd_eeprom_t));
+		if (rc) {
+			debug("DDR: failed to read SPD from address %u\n",
+			      SPD_EEPROM_ADDRESS);
+			memset(ctrl_dimms_spd, 0, sizeof(ddr2_spd_eeprom_t));
+		}
+	}
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
+			   unsigned int ctrl_num)
+{
+	popts->clk_adjust = 6;
+	popts->cpo_override = 7;
+	popts->write_data_delay = 3;
+	popts->half_strength_driver_enable = 0;
+}
+
+void pci_init_board(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* PCI is disabled */
+	out_be32(&gur->devdisr, in_be32(&gur->devdisr)
+				| MPC85xx_DEVDISR_PCI1
+				| MPC85xx_DEVDISR_PCI2
+				| MPC85xx_DEVDISR_PCIE);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+
+#endif
diff --git a/board/stx/stxamc8548/tlb.c b/board/stx/stxamc8548/tlb.c
new file mode 100644
index 0000000..fd2eaec
--- /dev/null
+++ b/board/stx/stxamc8548/tlb.c
@@ -0,0 +1,82 @@ 
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	256M	Non-cacheable, guarded
+	 * 0xf0000000	256M	LBC (FLASH included)
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE,
+		      CONFIG_SYS_LBC_OPTION_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 1:	1M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifdef CONFIG_SYS_SRIO1_MEM_PHYS
+	/*
+	 * TLB 2:       256M    Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:       256M    Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT + 0x10000000,
+		      CONFIG_SYS_SRIO1_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index 0f94969..7127b41 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -496,6 +496,7 @@  P2020RDB_SDCARD              powerpc     mpc85xx     p1_p2_rdb           freesca
 P2020RDB_SPIFLASH            powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020,SPIFLASH
 P4080DS                      powerpc     mpc85xx     corenet_ds          freescale
 mpq101                       powerpc     mpc85xx     mpq101              mercury        -           mpq101:SYS_LDSCRIPT=board/mercury/mpq101/u-boot.lds
+stxamc8548                   powerpc     mpc85xx     stxamc8548          stx            -           stxamc8548
 stxgp3                       powerpc     mpc85xx     stxgp3              stx
 stxssa                       powerpc     mpc85xx     stxssa              stx            -           stxssa
 stxssa_4M                    powerpc     mpc85xx     stxssa              stx            -           stxssa:STXSSA_4M
diff --git a/include/configs/stxamc8548.h b/include/configs/stxamc8548.h
new file mode 100644
index 0000000..e6eb799
--- /dev/null
+++ b/include/configs/stxamc8548.h
@@ -0,0 +1,374 @@ 
+/*
+ * Copyright 2011 Alex Dubov <oakad@yahoo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Merury Computers MPQ101 board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_36BIT
+# define CONFIG_PHYS_64BIT
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE      /* BOOKE */
+#define CONFIG_E500       /* BOOKE e500 family */
+#define CONFIG_MPC85xx    /* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8548    /* MPC8548 specific */
+#define CONFIG_MPQ101     /* MPQ101 board specific */
+
+#define CONFIG_SYS_SRIO   /* enable serial RapidIO */
+#define CONFIG_TSEC_ENET  /* tsec ethernet support */
+#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
+#define CONFIG_FSL_LAW    /* Use common FSL init code */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE   /* toggle L2 cache */
+#define CONFIG_BTB        /* toggle branch predition */
+
+#define CONFIG_PANIC_HANG
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_ADDR_MAP
+# define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
+#endif
+
+
+#define CONFIG_SYS_CLK_FREQ      33000000 /* sysclk for MPC85xx */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
+#define CONFIG_SYS_CCSRBAR         0xe0000000
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_SYS_CCSRBAR_PHYS   0xfe0000000ull
+#else
+# define CONFIG_SYS_CCSRBAR_PHYS   CONFIG_SYS_CCSRBAR
+#endif
+
+#define CONFIG_SYS_IMMR            CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#define CONFIG_DDR_SPD
+#define CONFIG_SPD_EEPROM
+#define CONFIG_DDR_2T_TIMING
+#define SPD_EEPROM_ADDRESS           0x50
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+
+#define CONFIG_MEM_INIT_VALUE        0xDeadBeef
+#define CONFIG_SYS_DDR_SDRAM_BASE    0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE        CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS   1
+#define CONFIG_DIMM_SLOTS_PER_CTLR   1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START     0x0ff00000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END       0x0ffffffc
+
+/*
+ * RAM definitions
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR   0xe4010000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE   0x4000     /* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
+				    - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET  CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN     (256 * 1024)  /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN      (1024 * 1024) /* Reserved for malloc */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
+
+
+/*
+ * FLASH on the Local Bus
+ * One bank, 16M, using the CFI driver.
+ */
+#define CONFIG_SYS_BOOT_BLOCK 0xff000000            /* boot TLB block */
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
+#else
+# define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#endif
+
+/* 0xff001801 */
+#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+			       | BR_PS_32 | BR_V)
+
+/* 0xff006e65 */
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(16) | OR_GPCM_XAM | OR_GPCM_CSNT \
+			       | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_6         \
+			       | OR_GPCM_TRLX | OR_GPCM_EAD)
+
+#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_FLASH_SHOW_PROGRESS     45   /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS     1    /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT      135  /* sectors per device */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT    60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    500   /* Flash Write Timeout (ms) */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash.
+ */
+#define CONFIG_ASSUME_AMD_FLASH
+
+/*
+ * Environment parameters
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_SECT_SIZE 0x4000   /* 16K boot sector */
+#define CONFIG_ENV_SIZE      0x4000
+
+/* Environment at the start of flash sector, before text. */
+#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x58000)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_TEXT_BASE    0xfffA0000
+
+/*
+ * Cypress CY7C67200 USB controller on the Local Bus.
+ * Not supported by u-boot at present.
+ */
+#define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_SYS_LBC_OPTION_BASE_PHYS 0xff0000000ull
+#else
+# define CONFIG_SYS_LBC_OPTION_BASE_PHYS CONFIG_SYS_LBC_OPTION_BASE
+#endif
+
+/* 0xf0001001 */
+#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBC_OPTION_BASE_PHYS) \
+			       | BR_PS_16 | BR_V)
+
+/* fffff002 */
+#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(0x8000) | OR_GPCM_XAM \
+			       | OR_GPCM_BCTLD | OR_GPCM_EHTR)
+
+/*
+ * Serial Ports
+ */
+#define CONFIG_CONS_INDEX           2
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK      get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE   {300, 600, 1200, 2400, 4800, 9600, \
+				     19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1     (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2     (CONFIG_SYS_CCSRBAR+0x4600)
+
+/*
+ * I2C buses and peripherals
+ */
+#define CONFIG_FSL_I2C         /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C        /* I2C with hardware support*/
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED   400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE   0x7f
+#define CONFIG_SYS_I2C_OFFSET  0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+
+/* I2C RTC - DS1339 */
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C_RTC_ADDR     0x68
+
+/* I2C EEPROM - 24C32 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR            0x51
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS     5
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN        2
+#define CONFIG_SYS_EEPROM_BUS_NUM             0
+
+/*
+ * RapidIO MMU
+ */
+#ifdef CONFIG_SYS_SRIO
+# define CONFIG_SRIO1
+# define CONFIG_SYS_SRIO1_MEM_VIRT  0xc0000000
+# define CONFIG_SYS_SRIO1_MEM_SIZE  0x20000000 /* 512M */
+
+# ifdef CONFIG_PHYS_64BIT
+#  define CONFIG_SYS_SRIO1_MEM_PHYS 0xfc0000000ull
+# else
+#  define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_VIRT
+# endif
+#endif
+
+/*
+ * Ethernet
+ */
+#ifdef CONFIG_TSEC_ENET
+
+# ifndef CONFIG_NET_MULTI
+#  define CONFIG_NET_MULTI
+# endif
+
+# define CONFIG_MII                /* MII PHY management */
+# define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
+
+# define CONFIG_TSEC1
+# define CONFIG_TSEC1_NAME       "eTSEC0"
+# define TSEC1_PHY_ADDR          0x10
+# define TSEC1_PHYIDX            0
+# define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+# define CONFIG_TSEC2
+# define CONFIG_TSEC2_NAME       "eTSEC1"
+# define TSEC2_PHY_ADDR          0x11
+# define TSEC2_PHYIDX            0
+# define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+# define CONFIG_TSEC3
+# define CONFIG_TSEC3_NAME       "eTSEC2"
+# define TSEC3_PHY_ADDR          0x12
+# define TSEC3_PHYIDX            0
+# define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+# define CONFIG_TSEC4
+# define CONFIG_TSEC4_NAME       "eTSEC3"
+# define TSEC4_PHY_ADDR          0x13
+# define TSEC4_PHYIDX            0
+# define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+/* Options are: eTSEC[0-3] */
+# define CONFIG_ETHPRIME         "eTSEC0"
+# define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_JFFS2
+
+/*
+ * Miscellaneous configurable options
+ */
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+#define CONFIG_FIT         /* new uImage format support */
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+#ifdef CONFIG_SYS_HUSH_PARSER
+# define CONFIG_SYS_PROMPT_HUSH_PS2  "> "
+#endif
+
+#define CONFIG_LOADS_ECHO            /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+#define CONFIG_SYS_LONGHELP          /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING       /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE         /* add autocompletion support */
+
+#define CONFIG_SYS_LOAD_ADDR         0x2000000    /* default load address */
+#define CONFIG_SYS_PROMPT            "AMC8548=> " /* Monitor Command Prompt */
+
+/* Console I/O Buffer Size */
+#ifdef CONFIG_CMD_KGDB
+# define CONFIG_SYS_CBSIZE 1024
+#else
+# define CONFIG_SYS_CBSIZE 256
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
+
+#define CONFIG_SYS_MAXARGS  16                /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ       1000              /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+# define CONFIG_KGDB_BAUDRATE  230400 /* speed to run kgdb serial port */
+# define CONFIG_KGDB_SER_INDEX 2      /* which serial port to use */
+#endif
+
+/*
+ * Basic Environment Configuration
+ */
+#define CONFIG_BAUDRATE  115200
+#define CONFIG_BOOTDELAY 5            /* -1 disables auto-boot */
+
+/*default location for tftp and bootm*/
+#define CONFIG_LOADADDR  CONFIG_SYS_LOAD_ADDR
+
+#endif /* __CONFIG_H */