From patchwork Tue Apr 12 06:17:44 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Rigby X-Patchwork-Id: 90709 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 5CA2DB6F1C for ; Tue, 12 Apr 2011 16:18:59 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5DF55280EB; Tue, 12 Apr 2011 08:18:50 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 11Nq92X9yidC; Tue, 12 Apr 2011 08:18:50 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id ACCC6280EE; Tue, 12 Apr 2011 08:18:35 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1C9EB280EB for ; Tue, 12 Apr 2011 08:18:34 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id V-FFwyZ5ewmT for ; Tue, 12 Apr 2011 08:18:33 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-iy0-f172.google.com (mail-iy0-f172.google.com [209.85.210.172]) by theia.denx.de (Postfix) with ESMTPS id 05D2E280ED for ; Tue, 12 Apr 2011 08:18:24 +0200 (CEST) Received: by iye19 with SMTP id 19so6381348iye.3 for ; Mon, 11 Apr 2011 23:18:23 -0700 (PDT) Received: by 10.42.139.5 with SMTP id e5mr8068902icu.136.1302589103241; Mon, 11 Apr 2011 23:18:23 -0700 (PDT) Received: from localhost.localdomain (c-76-23-54-220.hsd1.ut.comcast.net [76.23.54.220]) by mx.google.com with ESMTPS id i20sm4716910iby.31.2011.04.11.23.18.21 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 11 Apr 2011 23:18:22 -0700 (PDT) From: John Rigby To: u-boot@lists.denx.de Date: Tue, 12 Apr 2011 00:17:44 -0600 Message-Id: <1302589067-3688-2-git-send-email-john.rigby@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1301761196-26072-1-git-send-email-john.rigby@linaro.org> References: <1301761196-26072-1-git-send-email-john.rigby@linaro.org> Cc: Rabin Vincent , patches@linaro.org Subject: [U-Boot] [PATCHv3 1/4] Serial: p1011: new vendor init options X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Rabin Vincent Two new options: CONFIG_PL011_SERIAL_RLCR Some vendor versions of PL011 serial ports (e.g. ST-Ericsson U8500) have separate receive and transmit line control registers. Set this variable to initialize the extra register. CONFIG_PL011_SERIAL_FLUSH_ON_INIT On some platforms (e.g. U8500) U-Boot is loaded by a second stage boot loader that has already initialized the UART. Define this variable to flush the UART at init time. empty fifo on init Signed-off-by: Rabin Vincent Signed-off-by: John Rigby --- v3: Enable changes with new CONFIG_* options instead of platform. Document new CONFIG_* options in README. README | 12 ++++++++++++ drivers/serial/serial_pl01x.c | 17 +++++++++++++++-- drivers/serial/serial_pl01x.h | 4 ++++ 3 files changed, 31 insertions(+), 2 deletions(-) diff --git a/README b/README index c128a6c..8ccac6e 100644 --- a/README +++ b/README @@ -468,6 +468,18 @@ The following options need to be configured: define this to a list of base addresses for each (supported) port. See e.g. include/configs/versatile.h + CONFIG_PL011_SERIAL_RLCR + + Some vendor versions of PL011 serial ports (e.g. ST-Ericsson U8500) + have separate receive and transmit line control registers. Set + this variable to initialize the extra register. + + CONFIG_PL011_SERIAL_FLUSH_ON_INIT + + On some platforms (e.g. U8500) U-Boot is loaded by a second stage + boot loader that has already initialized the UART. Define this + variable to flush the UART at init time. + - Console Interface: Depending on board, define exactly one serial port diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index 5dfcde8..164b0ac 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -111,6 +111,15 @@ int serial_init (void) unsigned int divider; unsigned int remainder; unsigned int fraction; + unsigned int lcr; + +#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT + /* Empty RX fifo if necessary */ + if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) { + while (!(readl(®s->fr) & UART_PL01x_FR_RXFE)) + readl(®s->dr); + } +#endif /* First, disable everything */ writel(0, ®s->pl011_cr); @@ -131,9 +140,13 @@ int serial_init (void) writel(fraction, ®s->pl011_fbrd); /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */ - writel(UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN, - ®s->pl011_lcrh); + lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN; + writel(lcr, ®s->pl011_lcrh); +#ifdef CONFIG_PL011_SERIAL_RLCR + /* program receive line control register */ + writel(lcr, ®s->pl011_rlcr); +#endif /* Finally, enable the UART */ writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE, ®s->pl011_cr); diff --git a/drivers/serial/serial_pl01x.h b/drivers/serial/serial_pl01x.h index b670c24..96ee381 100644 --- a/drivers/serial/serial_pl01x.h +++ b/drivers/serial/serial_pl01x.h @@ -43,7 +43,11 @@ struct pl01x_regs { u32 pl010_lcrl; /* 0x10 Line control register, low byte */ u32 pl010_cr; /* 0x14 Control register */ u32 fr; /* 0x18 Flag register (Read only) */ +#ifdef CONFIG_PL011_SERIAL_RLCR + u32 pl011_rlcr; /* 0x1c Receive line control register */ +#else u32 reserved; +#endif u32 ilpr; /* 0x20 IrDA low-power counter register */ u32 pl011_ibrd; /* 0x24 Integer baud rate register */ u32 pl011_fbrd; /* 0x28 Fractional baud rate register */