Patchwork [U-Boot,v3] ARM: mx31: Print the silicon version

login
register
mail settings
Submitter Fabio Estevam
Date April 12, 2011, 12:22 a.m.
Message ID <1302567752-12651-1-git-send-email-festevam@gmail.com>
Download mbox | patch
Permalink /patch/90684/
State Superseded
Headers show

Comments

Fabio Estevam - April 12, 2011, 12:22 a.m.
Use the same method of the Linux kernel to print the MX31 silicon version on 
boot.

Tested on a MX31PDK with a 2.0 silicon, where it shows:

CPU:   Freescale i.MX31 at 531 MHz
MX31 silicon rev 2.0

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v2:
- Use macro instead of defines for IMX_CHIP_REVISION
Changes since v1:
- rename the CPU detect function name to get_cpu_rev
- Use struct to access iim register
 arch/arm/cpu/arm1136/mx31/generic.c       |   18 ++++++++++++++++
 arch/arm/include/asm/arch-mx31/imx-regs.h |   20 ++++++++++++++++++
 arch/arm/include/asm/imx_soc_revision.h   |   31 +++++++++++++++++++++++++++++
 3 files changed, 69 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/imx_soc_revision.h

Patch

diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c
index fa07fec..cfcb3d8 100644
--- a/arch/arm/cpu/arm1136/mx31/generic.c
+++ b/arch/arm/cpu/arm1136/mx31/generic.c
@@ -24,6 +24,7 @@ 
 #include <common.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/io.h>
+#include <asm/imx_soc_revision.h>
 
 static u32 mx31_decode_pll(u32 reg, u32 infreq)
 {
@@ -106,11 +107,28 @@  void mx31_set_pad(enum iomux_pins pin, u32 config)
 
 }
 
+void get_cpu_rev(void)
+{
+	u32 i, srev;
+
+	/* read SREV register from IIM module */
+	struct iim_regs *iim = (struct iim_regs *)MX31_IIM_BASE_ADDR;
+	srev = readl(&iim->iim_srev);
+
+	for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
+		if (srev == mx31_cpu_type[i].srev) {
+			printf("MX31 silicon rev %s\n", mx31_cpu_type[i].v);
+				return;
+		}
+	printf("Unknown CPU identifier. srev = %02x\n", srev);
+}
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo (void)
 {
 	printf("CPU:   Freescale i.MX31 at %d MHz\n",
 		mx31_get_mcu_main_clk() / 1000000);
+	get_cpu_rev();
 	return 0;
 }
 #endif
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 37337f2..6401a37 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -84,6 +84,24 @@  struct wdog_regs {
 	u16 wrsr;	/* Reset Status */
 };
 
+/* IIM Control Registers */
+struct iim_regs {
+	u32 iim_stat;
+	u32 iim_statm;
+	u32 iim_err;
+	u32 iim_emask;
+	u32 iim_fctl;
+	u32 iim_ua;
+	u32 iim_la;
+	u32 iim_sdat;
+	u32 iim_prev;
+	u32 iim_srev;
+	u32 iim_prog_p;
+	u32 iim_scs0;
+	u32 iim_scs1;
+	u32 iim_scs2;
+	u32 iim_scs3;
+};
 
 #define IOMUX_PADNUM_MASK	0x1ff
 #define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
@@ -480,6 +498,8 @@  enum iomux_pins {
 #define CCMR_FPM	(1 << 1)
 #define CCMR_CKIH	(2 << 1)
 
+#define MX31_IIM_BASE_ADDR	0x5001C000
+
 #define PDR0_CSI_PODF(x)	(((x) & 0x1ff) << 23)
 #define PDR0_PER_PODF(x)	(((x) & 0x1f) << 16)
 #define PDR0_HSP_PODF(x)	(((x) & 0x7) << 11)
diff --git a/arch/arm/include/asm/imx_soc_revision.h b/arch/arm/include/asm/imx_soc_revision.h
new file mode 100644
index 0000000..580b27e
--- /dev/null
+++ b/arch/arm/include/asm/imx_soc_revision.h
@@ -0,0 +1,31 @@ 
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ */
+
+#define IMX_CHIP_REVISION(maj, min)	((maj) * 16 + (min))
+
+
+struct mx3_cpu_type {
+	u8 srev;
+	const char *name;
+	const char *v;
+	unsigned int rev;
+};
+
+struct mx3_cpu_type mx31_cpu_type[] = {
+	{ .srev = 0x00, .name = "i.MX31(L)", .v = "1.0",  .rev = IMX_CHIP_REVISION(1, 0) },
+	{ .srev = 0x10, .name = "i.MX31",    .v = "1.1",  .rev = IMX_CHIP_REVISION(1, 1) },
+	{ .srev = 0x11, .name = "i.MX31L",   .v = "1.1",  .rev = IMX_CHIP_REVISION(1, 1) },
+	{ .srev = 0x12, .name = "i.MX31",    .v = "1.15", .rev = IMX_CHIP_REVISION(1, 1) },
+	{ .srev = 0x13, .name = "i.MX31L",   .v = "1.15", .rev = IMX_CHIP_REVISION(1, 1) },
+	{ .srev = 0x14, .name = "i.MX31",    .v = "1.2",  .rev = IMX_CHIP_REVISION(1, 2) },
+	{ .srev = 0x15, .name = "i.MX31L",   .v = "1.2",  .rev = IMX_CHIP_REVISION(1, 2) },
+	{ .srev = 0x28, .name = "i.MX31",    .v = "2.0",  .rev = IMX_CHIP_REVISION(2, 0) },
+	{ .srev = 0x29, .name = "i.MX31L",   .v = "2.0",  .rev = IMX_CHIP_REVISION(2, 0) },
+};