@@ -473,7 +473,6 @@ powerpc*-*-*)
extra_headers="${extra_headers} xmmintrin.h mm_malloc.h emmintrin.h"
extra_headers="${extra_headers} mmintrin.h x86intrin.h"
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h si2vmx.h"
- extra_headers="${extra_headers} paired.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
@@ -2502,11 +2501,11 @@ powerpc*-*-linux*)
all) maybe_biarch=yes ;;
esac
case ${target} in
- powerpc64*-*-linux*spe* | powerpc64*-*-linux*paired*)
+ powerpc64*-*-linux*spe* | powerpc*-*-linux*paired*)
echo "*** Configuration ${target} not supported" 1>&2
exit 1
;;
- powerpc*-*-linux*spe* | powerpc*-*-linux*paired*)
+ powerpc*-*-linux*spe*)
maybe_biarch=
;;
esac
@@ -2552,8 +2551,6 @@ powerpc*-*-linux*)
tm_file="${tm_file} rs6000/linuxaltivec.h" ;;
powerpc*-*-linux*spe*)
tm_file="${tm_file} ${cpu_type}/linuxspe.h ${cpu_type}/e500.h" ;;
- powerpc*-*-linux*paired*)
- tm_file="${tm_file} rs6000/750cl.h" ;;
esac
case ${target} in
*-linux*-musl*)
deleted file mode 100644
@@ -1,30 +0,0 @@
-/* Enable 750cl paired single support.
- Copyright (C) 2007-2018 Free Software Foundation, Inc.
- Contributed by Revital Eres (eres@il.ibm.com)
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published
- by the Free Software Foundation; either version 3, or (at your
- option) any later version.
-
- GCC is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- Under Section 7 of GPL version 3, you are granted additional
- permissions described in the GCC Runtime Library Exception, version
- 3.1, as published by the Free Software Foundation.
-
- You should have received a copy of the GNU General Public License and
- a copy of the GCC Runtime Library Exception along with this program;
- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
- <http://www.gnu.org/licenses/>. */
-
-#undef TARGET_PAIRED_FLOAT
-#define TARGET_PAIRED_FLOAT rs6000_paired_float
-
-#undef ASM_CPU_SPEC
-#define ASM_CPU_SPEC "-m750cl"
-
deleted file mode 100644
@@ -1,75 +0,0 @@
-/* PowerPC 750CL user include file.
- Copyright (C) 2007-2018 Free Software Foundation, Inc.
- Contributed by Revital Eres (eres@il.ibm.com).
-
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published
- by the Free Software Foundation; either version 3, or (at your
- option) any later version.
-
- GCC is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- Under Section 7 of GPL version 3, you are granted additional
- permissions described in the GCC Runtime Library Exception, version
- 3.1, as published by the Free Software Foundation.
-
- You should have received a copy of the GNU General Public License and
- a copy of the GCC Runtime Library Exception along with this program;
- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
- <http://www.gnu.org/licenses/>. */
-
-#ifndef _PAIRED_H
-#define _PAIRED_H
-
-#define vector __attribute__((vector_size(8)))
-
-#define paired_msub __builtin_paired_msub
-#define paired_madd __builtin_paired_madd
-#define paired_nmsub __builtin_paired_nmsub
-#define paired_nmadd __builtin_paired_nmadd
-#define paired_sum0 __builtin_paired_sum0
-#define paired_sum1 __builtin_paired_sum1
-#define paired_div __builtin_paired_divv2sf3
-#define paired_add __builtin_paired_addv2sf3
-#define paired_sub __builtin_paired_subv2sf3
-#define paired_mul __builtin_paired_mulv2sf3
-#define paired_muls0 __builtin_paired_muls0
-#define paired_muls1 __builtin_paired_muls1
-#define paired_madds0 __builtin_paired_madds0
-#define paired_madds1 __builtin_paired_madds1
-#define paired_merge00 __builtin_paired_merge00
-#define paired_merge01 __builtin_paired_merge01
-#define paired_merge10 __builtin_paired_merge10
-#define paired_merge11 __builtin_paired_merge11
-#define paired_abs __builtin_paired_absv2sf2
-#define paired_nabs __builtin_paired_nabsv2sf2
-#define paired_neg __builtin_paired_negv2sf2
-#define paired_sqrt __builtin_paired_sqrtv2sf2
-#define paired_res __builtin_paired_resv2sf2
-#define paired_stx __builtin_paired_stx
-#define paired_lx __builtin_paired_lx
-#define paired_cmpu0 __builtin_paired_cmpu0
-#define paired_cmpu1 __builtin_paired_cmpu1
-#define paired_sel __builtin_paired_selv2sf4
-
-/* Condition register codes for Paired predicates. */
-#define LT 0
-#define GT 1
-#define EQ 2
-#define UN 3
-
-#define paired_cmpu0_un(a,b) __builtin_paired_cmpu0 (UN, (a), (b))
-#define paired_cmpu0_eq(a,b) __builtin_paired_cmpu0 (EQ, (a), (b))
-#define paired_cmpu0_lt(a,b) __builtin_paired_cmpu0 (LT, (a), (b))
-#define paired_cmpu0_gt(a,b) __builtin_paired_cmpu0 (GT, (a), (b))
-#define paired_cmpu1_un(a,b) __builtin_paired_cmpu1 (UN, (a), (b))
-#define paired_cmpu1_eq(a,b) __builtin_paired_cmpu1 (EQ, (a), (b))
-#define paired_cmpu1_lt(a,b) __builtin_paired_cmpu1 (LT, (a), (b))
-#define paired_cmpu1_gt(a,b) __builtin_paired_cmpu1 (GT, (a), (b))
-
-#endif /* _PAIRED_H */
deleted file mode 100644
@@ -1,492 +0,0 @@
-;; PowerPC paired single and double hummer description
-;; Copyright (C) 2007-2018 Free Software Foundation, Inc.
-;; Contributed by David Edelsohn <edelsohn@gnu.org> and Revital Eres
-;; <eres@il.ibm.com>
-
-;; This file is part of GCC.
-
-;; GCC is free software; you can redistribute it and/or modify it
-;; under the terms of the GNU General Public License as published
-;; by the Free Software Foundation; either version 3, or (at your
-;; option) any later version.
-
-;; GCC is distributed in the hope that it will be useful, but WITHOUT
-;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
-;; License for more details.
-;;
-;; You should have received a copy of the GNU General Public License
-;; along with this program; see the file COPYING3. If not see
-;; <http://www.gnu.org/licenses/>.
-
-(define_c_enum "unspec"
- [UNSPEC_INTERHI_V2SF
- UNSPEC_INTERLO_V2SF
- UNSPEC_EXTEVEN_V2SF
- UNSPEC_EXTODD_V2SF
- ])
-
-(define_insn "negv2sf2"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")))]
- "TARGET_PAIRED_FLOAT"
- "ps_neg %0,%1"
- [(set_attr "type" "fp")])
-
-(define_insn "sqrtv2sf2"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (sqrt:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")))]
- "TARGET_PAIRED_FLOAT"
- "ps_rsqrte %0,%1"
- [(set_attr "type" "fp")])
-
-(define_insn "absv2sf2"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")))]
- "TARGET_PAIRED_FLOAT"
- "ps_abs %0,%1"
- [(set_attr "type" "fp")])
-
-(define_insn "nabsv2sf2"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (neg:V2SF (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f"))))]
- "TARGET_PAIRED_FLOAT"
- "ps_nabs %0,%1"
- [(set_attr "type" "fp")])
-
-(define_insn "addv2sf3"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "%f")
- (match_operand:V2SF 2 "gpc_reg_operand" "f")))]
- "TARGET_PAIRED_FLOAT"
- "ps_add %0,%1,%2"
- [(set_attr "type" "fp")])
-
-(define_insn "subv2sf3"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
- (match_operand:V2SF 2 "gpc_reg_operand" "f")))]
- "TARGET_PAIRED_FLOAT"
- "ps_sub %0,%1,%2"
- [(set_attr "type" "fp")])
-
-(define_insn "mulv2sf3"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "%f")
- (match_operand:V2SF 2 "gpc_reg_operand" "f")))]
- "TARGET_PAIRED_FLOAT"
- "ps_mul %0,%1,%2"
- [(set_attr "type" "fp")])
-
-(define_insn "resv2sf2"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
- "TARGET_PAIRED_FLOAT && flag_finite_math_only"
- "ps_res %0,%1"
- [(set_attr "type" "fp")])
-
-(define_insn "divv2sf3"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
- (match_operand:V2SF 2 "gpc_reg_operand" "f")))]
- "TARGET_PAIRED_FLOAT"
- "ps_div %0,%1,%2"
- [(set_attr "type" "sdiv")])
-
-(define_insn "paired_madds0"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (vec_concat:V2SF
- (fma:SF
- (vec_select:SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
- (parallel [(const_int 0)]))
- (vec_select:SF (match_operand:V2SF 2 "gpc_reg_operand" "f")
- (parallel [(const_int 0)]))
- (vec_select:SF (match_operand:V2SF 3 "gpc_reg_operand" "f")
- (parallel [(const_int 0)])))
- (fma:SF
- (vec_select:SF (match_dup 1)
- (parallel [(const_int 1)]))
- (vec_select:SF (match_dup 2)
- (parallel [(const_int 0)]))
- (vec_select:SF (match_dup 3)
- (parallel [(const_int 1)])))))]
- "TARGET_PAIRED_FLOAT"
- "ps_madds0 %0,%1,%2,%3"
- [(set_attr "type" "fp")])
-
-(define_insn "paired_madds1"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (vec_concat:V2SF
- (fma:SF
- (vec_select:SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
- (parallel [(const_int 0)]))
- (vec_select:SF (match_operand:V2SF 2 "gpc_reg_operand" "f")
- (parallel [(const_int 1)]))
- (vec_select:SF (match_operand:V2SF 3 "gpc_reg_operand" "f")
- (parallel [(const_int 0)])))
- (fma:SF
- (vec_select:SF (match_dup 1)
- (parallel [(const_int 1)]))
- (vec_select:SF (match_dup 2)
- (parallel [(const_int 1)]))
- (vec_select:SF (match_dup 3)
- (parallel [(const_int 1)])))))]
- "TARGET_PAIRED_FLOAT"
- "ps_madds1 %0,%1,%2,%3"
- [(set_attr "type" "fp")])
-
-(define_insn "*paired_madd"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (fma:V2SF
- (match_operand:V2SF 1 "gpc_reg_operand" "f")
- (match_operand:V2SF 2 "gpc_reg_operand" "f")
- (match_operand:V2SF 3 "gpc_reg_operand" "f")))]
- "TARGET_PAIRED_FLOAT"
- "ps_madd %0,%1,%2,%3"
- [(set_attr "type" "fp")])
-
-(define_insn "*paired_msub"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (fma:V2SF
- (match_operand:V2SF 1 "gpc_reg_operand" "f")
- (match_operand:V2SF 2 "gpc_reg_operand" "f")
- (neg:V2SF (match_operand:V2SF 3 "gpc_reg_operand" "f"))))]
- "TARGET_PAIRED_FLOAT"
- "ps_msub %0,%1,%2,%3"
- [(set_attr "type" "fp")])
-
-(define_insn "*paired_nmadd"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (neg:V2SF
- (fma:V2SF
- (match_operand:V2SF 1 "gpc_reg_operand" "f")
- (match_operand:V2SF 2 "gpc_reg_operand" "f")
- (match_operand:V2SF 3 "gpc_reg_operand" "f"))))]
- "TARGET_PAIRED_FLOAT"
- "ps_nmadd %0,%1,%2,%3"
- [(set_attr "type" "fp")])
-
-(define_insn "*paired_nmsub"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (neg:V2SF
- (fma:V2SF
- (match_operand:V2SF 1 "gpc_reg_operand" "f")
- (match_operand:V2SF 2 "gpc_reg_operand" "f")
- (neg:V2SF (match_operand:V2SF 3 "gpc_reg_operand" "f")))))]
- "TARGET_PAIRED_FLOAT"
- "ps_nmsub %0,%1,%2,%3"
- [(set_attr "type" "dmul")])
-
-(define_insn "selv2sf4"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (vec_concat:V2SF
- (if_then_else:SF (ge (vec_select:SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
- (parallel [(const_int 0)]))
- (match_operand:SF 4 "zero_fp_constant" "F"))
- (vec_select:SF (match_operand:V2SF 2 "gpc_reg_operand" "f")
- (parallel [(const_int 0)]))
- (vec_select:SF (match_operand:V2SF 3 "gpc_reg_operand" "f")
- (parallel [(const_int 0)])))
- (if_then_else:SF (ge (vec_select:SF (match_dup 1)
- (parallel [(const_int 1)]))
- (match_dup 4))
- (vec_select:SF (match_dup 2)
- (parallel [(const_int 1)]))
- (vec_select:SF (match_dup 3)
- (parallel [(const_int 1)])))))]
-
- "TARGET_PAIRED_FLOAT"
- "ps_sel %0,%1,%2,%3"
- [(set_attr "type" "fp")])
-
-(define_insn "*movv2sf_paired"
- [(set (match_operand:V2SF 0 "nonimmediate_operand" "=Z,f,f,Y,r,r,f")
- (match_operand:V2SF 1 "input_operand" "f,Z,f,r,Y,r,W"))]
- "TARGET_PAIRED_FLOAT
- && (register_operand (operands[0], V2SFmode)
- || register_operand (operands[1], V2SFmode))"
-{
- switch (which_alternative)
- {
- case 0: return "psq_stx %1,%y0,0,0";
- case 1: return "psq_lx %0,%y1,0,0";
- case 2: return "ps_mr %0,%1";
- case 3: return "#";
- case 4: return "#";
- case 5: return "#";
- case 6: return "#";
- default: gcc_unreachable ();
- }
-}
- [(set_attr "type" "fpstore,fpload,fp,*,*,*,*")])
-
-(define_insn "paired_stx"
- [(set (match_operand:V2SF 0 "memory_operand" "=Z")
- (match_operand:V2SF 1 "gpc_reg_operand" "f"))]
- "TARGET_PAIRED_FLOAT"
- "psq_stx %1,%y0,0,0"
- [(set_attr "type" "fpstore")])
-
-(define_insn "paired_lx"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (match_operand:V2SF 1 "memory_operand" "Z"))]
- "TARGET_PAIRED_FLOAT"
- "psq_lx %0,%y1,0,0"
- [(set_attr "type" "fpload")])
-
-
-(define_split
- [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
- (match_operand:V2SF 1 "input_operand" ""))]
- "TARGET_PAIRED_FLOAT && reload_completed
- && gpr_or_gpr_p (operands[0], operands[1])"
- [(pc)]
- {
- rs6000_split_multireg_move (operands[0], operands[1]); DONE;
- })
-
-(define_insn "paired_cmpu0"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (compare:CCFP (vec_select:SF
- (match_operand:V2SF 1 "gpc_reg_operand" "f")
- (parallel [(const_int 0)]))
- (vec_select:SF
- (match_operand:V2SF 2 "gpc_reg_operand" "f")
- (parallel [(const_int 0)]))))]
- "TARGET_PAIRED_FLOAT"
- "ps_cmpu0 %0,%1,%2"
- [(set_attr "type" "fpcompare")])
-
-(define_insn "paired_cmpu1"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (compare:CCFP (vec_select:SF
- (match_operand:V2SF 1 "gpc_reg_operand" "f")
- (parallel [(const_int 1)]))
- (vec_select:SF
- (match_operand:V2SF 2 "gpc_reg_operand" "f")
- (parallel [(const_int 1)]))))]
- "TARGET_PAIRED_FLOAT"
- "ps_cmpu1 %0,%1,%2"
- [(set_attr "type" "fpcompare")])
-
-(define_insn "paired_merge00"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (vec_select:V2SF
- (vec_concat:V4SF
- (match_operand:V2SF 1 "gpc_reg_operand" "f")
- (match_operand:V2SF 2 "gpc_reg_operand" "f"))
- (parallel [(const_int 0) (const_int 2)])))]
- "TARGET_PAIRED_FLOAT"
- "ps_merge00 %0, %1, %2"
- [(set_attr "type" "fp")])
-
-(define_insn "paired_merge01"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (vec_select:V2SF
- (vec_concat:V4SF
- (match_operand:V2SF 1 "gpc_reg_operand" "f")
- (match_operand:V2SF 2 "gpc_reg_operand" "f"))
- (parallel [(const_int 0) (const_int 3)])))]
- "TARGET_PAIRED_FLOAT"
- "ps_merge01 %0, %1, %2"
- [(set_attr "type" "fp")])
-
-(define_insn "paired_merge10"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (vec_select:V2SF
- (vec_concat:V4SF
- (match_operand:V2SF 1 "gpc_reg_operand" "f")
- (match_operand:V2SF 2 "gpc_reg_operand" "f"))
- (parallel [(const_int 1) (const_int 2)])))]
- "TARGET_PAIRED_FLOAT"
- "ps_merge10 %0, %1, %2"
- [(set_attr "type" "fp")])
-
-(define_insn "paired_merge11"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (vec_select:V2SF
- (vec_concat:V4SF
- (match_operand:V2SF 1 "gpc_reg_operand" "f")
- (match_operand:V2SF 2 "gpc_reg_operand" "f"))
- (parallel [(const_int 1) (const_int 3)])))]
- "TARGET_PAIRED_FLOAT"
- "ps_merge11 %0, %1, %2"
- [(set_attr "type" "fp")])
-
-(define_insn "paired_sum0"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (vec_concat:V2SF (plus:SF (vec_select:SF
- (match_operand:V2SF 1 "gpc_reg_operand" "f")
- (parallel [(const_int 0)]))
- (vec_select:SF
- (match_operand:V2SF 2 "gpc_reg_operand" "f")
- (parallel [(const_int 1)])))
- (vec_select:SF
- (match_operand:V2SF 3 "gpc_reg_operand" "f")
- (parallel [(const_int 1)]))))]
- "TARGET_PAIRED_FLOAT"
- "ps_sum0 %0,%1,%2,%3"
- [(set_attr "type" "fp")])
-
-(define_insn "paired_sum1"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (vec_concat:V2SF (vec_select:SF
- (match_operand:V2SF 2 "gpc_reg_operand" "f")
- (parallel [(const_int 1)]))
- (plus:SF (vec_select:SF
- (match_operand:V2SF 1 "gpc_reg_operand" "f")
- (parallel [(const_int 0)]))
- (vec_select:SF
- (match_operand:V2SF 3 "gpc_reg_operand" "f")
- (parallel [(const_int 1)])))))]
- "TARGET_PAIRED_FLOAT"
- "ps_sum1 %0,%1,%2,%3"
- [(set_attr "type" "fp")])
-
-(define_insn "paired_muls0"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (mult:V2SF (match_operand:V2SF 2 "gpc_reg_operand" "f")
- (vec_duplicate:V2SF
- (vec_select:SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
- (parallel [(const_int 0)])))))]
- "TARGET_PAIRED_FLOAT"
- "ps_muls0 %0, %1, %2"
- [(set_attr "type" "fp")])
-
-
-(define_insn "paired_muls1"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (mult:V2SF (match_operand:V2SF 2 "gpc_reg_operand" "f")
- (vec_duplicate:V2SF
- (vec_select:SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
- (parallel [(const_int 1)])))))]
- "TARGET_PAIRED_FLOAT"
- "ps_muls1 %0, %1, %2"
- [(set_attr "type" "fp")])
-
-(define_expand "vec_initv2sfsf"
- [(match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (match_operand 1 "" "")]
- "TARGET_PAIRED_FLOAT"
-{
- paired_expand_vector_init (operands[0], operands[1]);
- DONE;
-})
-
-(define_insn "*vconcatsf"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (vec_concat:V2SF
- (match_operand:SF 1 "gpc_reg_operand" "f")
- (match_operand:SF 2 "gpc_reg_operand" "f")))]
- "TARGET_PAIRED_FLOAT"
- "ps_merge00 %0, %1, %2"
- [(set_attr "type" "fp")])
-
-(define_expand "sminv2sf3"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (smin:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
- (match_operand:V2SF 2 "gpc_reg_operand" "f")))]
- "TARGET_PAIRED_FLOAT"
-{
- rtx tmp = gen_reg_rtx (V2SFmode);
-
- emit_insn (gen_subv2sf3 (tmp, operands[1], operands[2]));
- emit_insn (gen_selv2sf4 (operands[0], tmp, operands[2], operands[1], CONST0_RTX (SFmode)));
- DONE;
-})
-
-(define_expand "smaxv2sf3"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (smax:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
- (match_operand:V2SF 2 "gpc_reg_operand" "f")))]
- "TARGET_PAIRED_FLOAT"
-{
- rtx tmp = gen_reg_rtx (V2SFmode);
-
- emit_insn (gen_subv2sf3 (tmp, operands[1], operands[2]));
- emit_insn (gen_selv2sf4 (operands[0], tmp, operands[1], operands[2], CONST0_RTX (SFmode)));
- DONE;
-})
-
-(define_expand "reduc_smax_scal_v2sf"
- [(match_operand:SF 0 "gpc_reg_operand" "=f")
- (match_operand:V2SF 1 "gpc_reg_operand" "f")]
- "TARGET_PAIRED_FLOAT"
-{
- rtx tmp_swap = gen_reg_rtx (V2SFmode);
- rtx tmp = gen_reg_rtx (V2SFmode);
- rtx vec_res = gen_reg_rtx (V2SFmode);
- rtx di_res = gen_reg_rtx (DImode);
-
- emit_insn (gen_paired_merge10 (tmp_swap, operands[1], operands[1]));
- emit_insn (gen_subv2sf3 (tmp, operands[1], tmp_swap));
- emit_insn (gen_selv2sf4 (vec_res, tmp, operands[1], tmp_swap,
- CONST0_RTX (SFmode)));
- emit_move_insn (di_res, simplify_gen_subreg (DImode, vec_res, V2SFmode, 0));
- emit_move_insn (operands[0], simplify_gen_subreg (SFmode, di_res, DImode,
- BYTES_BIG_ENDIAN ? 4 : 0));
-
- DONE;
-})
-
-(define_expand "reduc_smin_scal_v2sf"
- [(match_operand:SF 0 "gpc_reg_operand" "=f")
- (match_operand:V2SF 1 "gpc_reg_operand" "f")]
- "TARGET_PAIRED_FLOAT"
-{
- rtx tmp_swap = gen_reg_rtx (V2SFmode);
- rtx tmp = gen_reg_rtx (V2SFmode);
- rtx vec_res = gen_reg_rtx (V2SFmode);
- rtx di_res = gen_reg_rtx (DImode);
-
- emit_insn (gen_paired_merge10 (tmp_swap, operands[1], operands[1]));
- emit_insn (gen_subv2sf3 (tmp, operands[1], tmp_swap));
- emit_insn (gen_selv2sf4 (vec_res, tmp, tmp_swap, operands[1],
- CONST0_RTX (SFmode)));
- emit_move_insn (di_res, simplify_gen_subreg (DImode, vec_res, V2SFmode, 0));
- emit_move_insn (operands[0], simplify_gen_subreg (SFmode, di_res, DImode,
- BYTES_BIG_ENDIAN ? 4 : 0));
-
- DONE;
-})
-
-(define_expand "reduc_plus_scal_v2sf"
- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
- (match_operand:V2SF 1 "gpc_reg_operand" "f"))]
- "TARGET_PAIRED_FLOAT"
-{
- rtx vec_res = gen_reg_rtx (V2SFmode);
- rtx di_res = gen_reg_rtx (DImode);
-
- emit_insn (gen_paired_sum1 (vec_res, operands[1], operands[1], operands[1]));
- emit_move_insn (di_res, simplify_gen_subreg (DImode, vec_res, V2SFmode, 0));
- emit_move_insn (operands[0], simplify_gen_subreg (SFmode, di_res, DImode,
- BYTES_BIG_ENDIAN ? 4 : 0));
- DONE;
-})
-
-(define_expand "movmisalignv2sf"
- [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
- (match_operand:V2SF 1 "any_operand" ""))]
- "TARGET_PAIRED_FLOAT"
-{
- paired_expand_vector_move (operands);
- DONE;
-})
-
-(define_expand "vcondv2sfv2sf"
- [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
- (if_then_else:V2SF
- (match_operator 3 "gpc_reg_operand"
- [(match_operand:V2SF 4 "gpc_reg_operand" "f")
- (match_operand:V2SF 5 "gpc_reg_operand" "f")])
- (match_operand:V2SF 1 "gpc_reg_operand" "f")
- (match_operand:V2SF 2 "gpc_reg_operand" "f")))]
- "TARGET_PAIRED_FLOAT && flag_unsafe_math_optimizations"
-{
- if (paired_emit_vector_cond_expr (operands[0], operands[1], operands[2],
- operands[3], operands[4], operands[5]))
- DONE;
- else
- FAIL;
-})
@@ -690,11 +690,6 @@ (define_predicate "xxspltib_constant_nosplit"
(define_predicate "easy_vector_constant"
(match_code "const_vector")
{
- /* As the paired vectors are actually FPRs it seems that there is
- no easy way to load a CONST_VECTOR without using memory. */
- if (TARGET_PAIRED_FLOAT)
- return false;
-
/* Because IEEE 128-bit floating point is considered a vector type
in order to pass it in VSX registers, it might use this function
instead of easy_fp_constant. */
@@ -32,7 +32,6 @@
RS6000_BUILTIN_D -- DST builtins
RS6000_BUILTIN_H -- HTM builtins
RS6000_BUILTIN_P -- Altivec, VSX, ISA 2.07 vector predicate builtins
- RS6000_BUILTIN_Q -- Paired floating point VSX predicate builtins
RS6000_BUILTIN_X -- special builtins
Each of the above macros takes 4 arguments:
@@ -74,10 +73,6 @@
#error "RS6000_BUILTIN_P is not defined."
#endif
-#ifndef RS6000_BUILTIN_Q
- #error "RS6000_BUILTIN_Q is not defined."
-#endif
-
#ifndef RS6000_BUILTIN_X
#error "RS6000_BUILTIN_X is not defined."
#endif
@@ -549,47 +544,6 @@
| RS6000_BTC_VOID), \
CODE_FOR_ ## ICODE) /* ICODE */
-/* Paired floating point convenience macros. */
-#define BU_PAIRED_1(ENUM, NAME, ATTR, ICODE) \
- RS6000_BUILTIN_1 (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \
- "__builtin_paired_" NAME, /* NAME */ \
- RS6000_BTM_PAIRED, /* MASK */ \
- (RS6000_BTC_ ## ATTR /* ATTR */ \
- | RS6000_BTC_UNARY), \
- CODE_FOR_ ## ICODE) /* ICODE */
-
-#define BU_PAIRED_2(ENUM, NAME, ATTR, ICODE) \
- RS6000_BUILTIN_2 (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \
- "__builtin_paired_" NAME, /* NAME */ \
- RS6000_BTM_PAIRED, /* MASK */ \
- (RS6000_BTC_ ## ATTR /* ATTR */ \
- | RS6000_BTC_BINARY), \
- CODE_FOR_ ## ICODE) /* ICODE */
-
-#define BU_PAIRED_3(ENUM, NAME, ATTR, ICODE) \
- RS6000_BUILTIN_3 (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \
- "__builtin_paired_" NAME, /* NAME */ \
- RS6000_BTM_PAIRED, /* MASK */ \
- (RS6000_BTC_ ## ATTR /* ATTR */ \
- | RS6000_BTC_TERNARY), \
- CODE_FOR_ ## ICODE) /* ICODE */
-
-#define BU_PAIRED_P(ENUM, NAME, ATTR, ICODE) \
- RS6000_BUILTIN_Q (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \
- "__builtin_paired_" NAME, /* NAME */ \
- RS6000_BTM_PAIRED, /* MASK */ \
- (RS6000_BTC_ ## ATTR /* ATTR */ \
- | RS6000_BTC_PREDICATE), \
- CODE_FOR_ ## ICODE) /* ICODE */
-
-#define BU_PAIRED_X(ENUM, NAME, ATTR) \
- RS6000_BUILTIN_X (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \
- "__builtin_paired_" NAME, /* NAME */ \
- RS6000_BTM_PAIRED, /* MASK */ \
- (RS6000_BTC_ ## ATTR /* ATTR */ \
- | RS6000_BTC_SPECIAL), \
- CODE_FOR_nothing) /* ICODE */
-
#define BU_SPECIAL_X(ENUM, NAME, MASK, ATTR) \
RS6000_BUILTIN_X (ENUM, /* ENUM */ \
NAME, /* NAME */ \
@@ -2481,44 +2435,6 @@ BU_HTM_0 (GET_TEXASRU, "get_texasru", SPR, nothing)
BU_HTM_V1 (SET_TEXASRU, "set_texasru", SPR, nothing)
-/* 3 argument paired floating point builtins. */
-BU_PAIRED_3 (MSUB, "msub", FP, fmsv2sf4)
-BU_PAIRED_3 (MADD, "madd", FP, fmav2sf4)
-BU_PAIRED_3 (MADDS0, "madds0", FP, paired_madds0)
-BU_PAIRED_3 (MADDS1, "madds1", FP, paired_madds1)
-BU_PAIRED_3 (NMSUB, "nmsub", FP, nfmsv2sf4)
-BU_PAIRED_3 (NMADD, "nmadd", FP, nfmav2sf4)
-BU_PAIRED_3 (SUM0, "sum0", FP, paired_sum0)
-BU_PAIRED_3 (SUM1, "sum1", FP, paired_sum1)
-BU_PAIRED_3 (SELV2SF4, "selv2sf4", CONST, selv2sf4)
-
-/* 2 argument paired floating point builtins. */
-BU_PAIRED_2 (DIVV2SF3, "divv2sf3", FP, divv2sf3)
-BU_PAIRED_2 (ADDV2SF3, "addv2sf3", FP, addv2sf3)
-BU_PAIRED_2 (SUBV2SF3, "subv2sf3", FP, subv2sf3)
-BU_PAIRED_2 (MULV2SF3, "mulv2sf3", FP, mulv2sf3)
-BU_PAIRED_2 (MULS0, "muls0", FP, paired_muls0)
-BU_PAIRED_2 (MULS1, "muls1", FP, paired_muls1)
-BU_PAIRED_2 (MERGE00, "merge00", CONST, paired_merge00)
-BU_PAIRED_2 (MERGE01, "merge01", CONST, paired_merge01)
-BU_PAIRED_2 (MERGE10, "merge10", CONST, paired_merge10)
-BU_PAIRED_2 (MERGE11, "merge11", CONST, paired_merge11)
-
-/* 1 argument paired floating point builtin functions. */
-BU_PAIRED_1 (ABSV2SF2, "absv2sf2", CONST, absv2sf2)
-BU_PAIRED_1 (NABSV2SF2, "nabsv2sf2", CONST, nabsv2sf2)
-BU_PAIRED_1 (NEGV2SF2, "negv2sf2", CONST, negv2sf2)
-BU_PAIRED_1 (SQRTV2SF2, "sqrtv2sf2", FP, sqrtv2sf2)
-BU_PAIRED_1 (RESV2SF, "resv2sf2", FP, resv2sf2)
-
-/* PAIRED builtins that are handled as special cases. */
-BU_PAIRED_X (STX, "stx", MISC)
-BU_PAIRED_X (LX, "lx", MISC)
-
-/* Paired predicates. */
-BU_PAIRED_P (CMPU0, "cmpu0", CONST, paired_cmpu0)
-BU_PAIRED_P (CMPU1, "cmpu1", CONST, paired_cmpu1)
-
/* Power7 builtins, that aren't VSX instructions. */
BU_SPECIAL_X (POWER7_BUILTIN_BPERMD, "__builtin_bpermd", RS6000_BTM_POPCNTD,
RS6000_BTC_CONST)
@@ -494,17 +494,14 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
or TARGET_DOUBLE_FLOAT are turned off. Hereafter, the
OPTION_MASK_VSX flag is considered to have been turned off
explicitly.
- 3. If TARGET_PAIRED_FLOAT was enabled. Hereafter, the
- OPTION_MASK_VSX flag is considered to have been turned off
- explicitly.
- 4. If TARGET_AVOID_XFORM is turned on explicitly at the outermost
+ 3. If TARGET_AVOID_XFORM is turned on explicitly at the outermost
compilation context, or if it is turned on by any means in an
inner compilation context. Hereafter, the OPTION_MASK_VSX
flag is considered to have been turned off explicitly.
- 5. If TARGET_ALTIVEC was explicitly disabled. Hereafter, the
+ 4. If TARGET_ALTIVEC was explicitly disabled. Hereafter, the
OPTION_MASK_VSX flag is considered to have been turned off
explicitly.
- 6. If an inner context (as introduced by
+ 5. If an inner context (as introduced by
__attribute__((__target__())) or #pragma GCC target()
requests a target that normally enables the
OPTION_MASK_VSX flag but the outer-most "main target"
@@ -590,10 +587,6 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
rs6000_define_or_undefine_macro (define_p, "__FLOAT128_HARDWARE__");
/* options from the builtin masks. */
- /* Note that RS6000_BTM_PAIRED is enabled only if
- TARGET_PAIRED_FLOAT is enabled (e.g. -mpaired). */
- if ((bu_mask & RS6000_BTM_PAIRED) != 0)
- rs6000_define_or_undefine_macro (define_p, "__PAIRED__");
/* Note that RS6000_BTM_CELL is enabled only if (rs6000_cpu ==
PROCESSOR_CELL) (e.g. -mcpu=cell). */
if ((bu_mask & RS6000_BTM_CELL) != 0)
@@ -51,10 +51,6 @@ VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */
VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */
VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */
-/* Paired single. */
-VECTOR_MODE (FLOAT, SF, 2); /* The only valid paired-single mode. */
-VECTOR_MODE (INT, SI, 2); /* For paired-single permutes. */
-
/* Replacement for TImode that only is allowed in GPRs. We also use PTImode
for quad memory atomic operations to force getting an even/odd register
combination. */
@@ -149,7 +149,6 @@ enum rs6000_vector {
VECTOR_ALTIVEC, /* Use altivec for vector processing */
VECTOR_VSX, /* Use VSX for vector processing */
VECTOR_P8_VECTOR, /* Use ISA 2.07 VSX for vector processing */
- VECTOR_PAIRED, /* Use paired floating point for vectors */
VECTOR_OTHER /* Some other vector unit */
};
@@ -57,7 +57,6 @@ extern bool rs6000_move_128bit_ok_p (rtx []);
extern bool rs6000_split_128bit_ok_p (rtx []);
extern void rs6000_expand_float128_convert (rtx, rtx, bool);
extern void rs6000_expand_vector_init (rtx, rtx);
-extern void paired_expand_vector_init (rtx, rtx);
extern void rs6000_expand_vector_set (rtx, rtx, int);
extern void rs6000_expand_vector_extract (rtx, rtx, rtx);
extern void rs6000_split_vec_extract_var (rtx, rtx, rtx, rtx, rtx);
@@ -110,9 +109,6 @@ extern enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
rtx);
extern void rs6000_secondary_reload_inner (rtx, rtx, rtx, bool);
extern void rs6000_secondary_reload_gpr (rtx, rtx, rtx, bool);
-extern int paired_emit_vector_cond_expr (rtx, rtx, rtx,
- rtx, rtx, rtx);
-extern void paired_expand_vector_move (rtx operands[]);
extern int ccr_bit (rtx, int);
@@ -1271,7 +1271,6 @@ struct processor_costs ppca2_cost = {
#undef RS6000_BUILTIN_D
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
#undef RS6000_BUILTIN_X
#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
@@ -1298,9 +1297,6 @@ struct processor_costs ppca2_cost = {
#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
{ NAME, ICODE, MASK, ATTR },
-#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
- { NAME, ICODE, MASK, ATTR },
-
#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
{ NAME, ICODE, MASK, ATTR },
@@ -1324,7 +1320,6 @@ static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
#undef RS6000_BUILTIN_D
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
#undef RS6000_BUILTIN_X
/* Support for -mveclibabi=<xxx> to control which vector library to use. */
@@ -1359,8 +1354,6 @@ static tree builtin_function_type (machine_mode, machine_mode,
machine_mode, machine_mode,
enum rs6000_builtins, const char *name);
static void rs6000_common_init_builtins (void);
-static void paired_init_builtins (void);
-static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);
static void htm_init_builtins (void);
static rs6000_stack_t *rs6000_stack_info (void);
static void is_altivec_return_reg (rtx, void *);
@@ -2117,10 +2110,6 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
return 1;
}
- if (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT
- && PAIRED_VECTOR_MODE (mode))
- return 1;
-
return 0;
}
@@ -2190,11 +2179,6 @@ rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)
if (GET_MODE_CLASS (mode2) == MODE_CC)
return false;
- if (PAIRED_VECTOR_MODE (mode1))
- return PAIRED_VECTOR_MODE (mode2);
- if (PAIRED_VECTOR_MODE (mode2))
- return false;
-
return true;
}
@@ -2311,7 +2295,6 @@ rs6000_debug_vector_unit (enum rs6000_vector v)
case VECTOR_ALTIVEC: ret = "altivec"; break;
case VECTOR_VSX: ret = "vsx"; break;
case VECTOR_P8_VECTOR: ret = "p8_vector"; break;
- case VECTOR_PAIRED: ret = "paired"; break;
case VECTOR_OTHER: ret = "other"; break;
default: ret = "unknown"; break;
}
@@ -2525,7 +2508,6 @@ rs6000_debug_reg_global (void)
SDmode,
DDmode,
TDmode,
- V2SImode,
V16QImode,
V8HImode,
V4SImode,
@@ -2536,7 +2518,6 @@ rs6000_debug_reg_global (void)
V8SImode,
V4DImode,
V2TImode,
- V2SFmode,
V4SFmode,
V2DFmode,
V8SFmode,
@@ -3257,8 +3238,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
rs6000_vector_align[TImode] = align64;
}
- /* TODO add paired floating point vector support. */
-
/* Register class constraints for the constraints that depend on compile
switches. When the VSX code was added, different constraints were added
based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
@@ -3896,7 +3875,7 @@ darwin_rs6000_override_options (void)
/* Return the builtin mask of the various options used that could affect which
builtins were used. In the past we used target_flags, but we've run out of
- bits, and some options like PAIRED are no longer in target_flags. */
+ bits, and some options are no longer in target_flags. */
HOST_WIDE_INT
rs6000_builtin_mask_calculate (void)
@@ -3904,7 +3883,6 @@ rs6000_builtin_mask_calculate (void)
return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)
| ((TARGET_CMPB) ? RS6000_BTM_CMPB : 0)
| ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
- | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0)
| ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
| ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
| ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)
@@ -4277,8 +4255,6 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
}
}
- else if (TARGET_PAIRED_FLOAT)
- msg = N_("-mvsx and -mpaired are incompatible");
else if (TARGET_AVOID_XFORM > 0)
msg = N_("-mvsx needs indexed addressing");
else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit
@@ -5266,7 +5242,7 @@ rs6000_option_override_internal (bool global_init_p)
/* Set the builtin mask of the various options used that could affect which
builtins were used. In the past we used target_flags, but we've run out
- of bits, and some options like PAIRED are no longer in target_flags. */
+ of bits, and some options are no longer in target_flags. */
rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
rs6000_print_builtin_options (stderr, 0, "builtin mask",
@@ -5593,9 +5569,6 @@ rs6000_preferred_simd_mode (scalar_mode mode)
return V16QImode;
default:;
}
- if (TARGET_PAIRED_FLOAT
- && mode == SFmode)
- return V2SFmode;
return word_mode;
}
@@ -6272,8 +6245,8 @@ num_insns_constant (rtx op, machine_mode mode)
/* Interpret element ELT of the CONST_VECTOR OP as an integer value.
If the mode of OP is MODE_VECTOR_INT, this simply returns the
- corresponding element of the vector, but for V4SFmode and V2SFmode,
- the corresponding "float" is interpreted as an SImode integer. */
+ corresponding element of the vector, but for V4SFmode, the
+ corresponding "float" is interpreted as an SImode integer. */
HOST_WIDE_INT
const_vector_elt_as_int (rtx op, unsigned int elt)
@@ -6285,8 +6258,7 @@ const_vector_elt_as_int (rtx op, unsigned int elt)
&& GET_MODE (op) != V2DFmode);
tmp = CONST_VECTOR_ELT (op, elt);
- if (GET_MODE (op) == V4SFmode
- || GET_MODE (op) == V2SFmode)
+ if (GET_MODE (op) == V4SFmode)
tmp = gen_lowpart (SImode, tmp);
return INTVAL (tmp);
}
@@ -6790,156 +6762,6 @@ output_vec_const_move (rtx *operands)
gcc_unreachable ();
}
-/* Initialize TARGET of vector PAIRED to VALS. */
-
-void
-paired_expand_vector_init (rtx target, rtx vals)
-{
- machine_mode mode = GET_MODE (target);
- int n_elts = GET_MODE_NUNITS (mode);
- int n_var = 0;
- rtx x, new_rtx, tmp, constant_op, op1, op2;
- int i;
-
- for (i = 0; i < n_elts; ++i)
- {
- x = XVECEXP (vals, 0, i);
- if (!(CONST_SCALAR_INT_P (x) || CONST_DOUBLE_P (x) || CONST_FIXED_P (x)))
- ++n_var;
- }
- if (n_var == 0)
- {
- /* Load from constant pool. */
- emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
- return;
- }
-
- if (n_var == 2)
- {
- /* The vector is initialized only with non-constants. */
- new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, XVECEXP (vals, 0, 0),
- XVECEXP (vals, 0, 1));
-
- emit_move_insn (target, new_rtx);
- return;
- }
-
- /* One field is non-constant and the other one is a constant. Load the
- constant from the constant pool and use ps_merge instruction to
- construct the whole vector. */
- op1 = XVECEXP (vals, 0, 0);
- op2 = XVECEXP (vals, 0, 1);
-
- constant_op = (CONSTANT_P (op1)) ? op1 : op2;
-
- tmp = gen_reg_rtx (GET_MODE (constant_op));
- emit_move_insn (tmp, constant_op);
-
- if (CONSTANT_P (op1))
- new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, tmp, op2);
- else
- new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, op1, tmp);
-
- emit_move_insn (target, new_rtx);
-}
-
-void
-paired_expand_vector_move (rtx operands[])
-{
- rtx op0 = operands[0], op1 = operands[1];
-
- emit_move_insn (op0, op1);
-}
-
-/* Emit vector compare for code RCODE. DEST is destination, OP1 and
- OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
- operands for the relation operation COND. This is a recursive
- function. */
-
-static void
-paired_emit_vector_compare (enum rtx_code rcode,
- rtx dest, rtx op0, rtx op1,
- rtx cc_op0, rtx cc_op1)
-{
- rtx tmp = gen_reg_rtx (V2SFmode);
- rtx tmp1, max, min;
-
- gcc_assert (TARGET_PAIRED_FLOAT);
- gcc_assert (GET_MODE (op0) == GET_MODE (op1));
-
- switch (rcode)
- {
- case LT:
- case LTU:
- paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
- return;
- case GE:
- case GEU:
- emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
- emit_insn (gen_selv2sf4 (dest, tmp, op0, op1, CONST0_RTX (SFmode)));
- return;
- case LE:
- case LEU:
- paired_emit_vector_compare (GE, dest, op0, op1, cc_op1, cc_op0);
- return;
- case GT:
- paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
- return;
- case EQ:
- tmp1 = gen_reg_rtx (V2SFmode);
- max = gen_reg_rtx (V2SFmode);
- min = gen_reg_rtx (V2SFmode);
- gen_reg_rtx (V2SFmode);
-
- emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
- emit_insn (gen_selv2sf4
- (max, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
- emit_insn (gen_subv2sf3 (tmp, cc_op1, cc_op0));
- emit_insn (gen_selv2sf4
- (min, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
- emit_insn (gen_subv2sf3 (tmp1, min, max));
- emit_insn (gen_selv2sf4 (dest, tmp1, op0, op1, CONST0_RTX (SFmode)));
- return;
- case NE:
- paired_emit_vector_compare (EQ, dest, op1, op0, cc_op0, cc_op1);
- return;
- case UNLE:
- paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
- return;
- case UNLT:
- paired_emit_vector_compare (LT, dest, op1, op0, cc_op0, cc_op1);
- return;
- case UNGE:
- paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
- return;
- case UNGT:
- paired_emit_vector_compare (GT, dest, op1, op0, cc_op0, cc_op1);
- return;
- default:
- gcc_unreachable ();
- }
-
- return;
-}
-
-/* Emit vector conditional expression.
- DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
- CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
-
-int
-paired_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
- rtx cond, rtx cc_op0, rtx cc_op1)
-{
- enum rtx_code rcode = GET_CODE (cond);
-
- if (!TARGET_PAIRED_FLOAT)
- return 0;
-
- paired_emit_vector_compare (rcode, dest, op1, op2, cc_op0, cc_op1);
-
- return 1;
-}
-
/* Initialize vector TARGET to VALS. */
void
@@ -7869,16 +7691,8 @@ rs6000_data_alignment (tree type, unsigned int align, enum data_align how)
{
if (how != align_opt)
{
- if (TREE_CODE (type) == VECTOR_TYPE)
- {
- if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (type)))
- {
- if (align < 64)
- align = 64;
- }
- else if (align < 128)
- align = 128;
- }
+ if (TREE_CODE (type) == VECTOR_TYPE && align < 128)
+ align = 128;
}
if (how != align_abi)
@@ -8293,13 +8107,6 @@ reg_offset_addressing_ok_p (machine_mode mode)
return mode_supports_vsx_dform_quad (mode);
break;
- case E_V2SImode:
- case E_V2SFmode:
- /* Paired vector modes. Only reg+reg addressing is valid. */
- if (TARGET_PAIRED_FLOAT)
- return false;
- break;
-
case E_SDmode:
/* If we can do direct load/stores of SDmode, restrict it to reg+reg
addressing for the LFIWZX and STFIWX instructions. */
@@ -8541,11 +8348,6 @@ rs6000_legitimate_offset_address_p (machine_mode mode, rtx x,
extra = 0;
switch (mode)
{
- case E_V2SImode:
- case E_V2SFmode:
- /* Paired single modes: offset addressing isn't valid. */
- return false;
-
case E_DFmode:
case E_DDmode:
case E_DImode:
@@ -8763,8 +8565,7 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
&& GET_CODE (XEXP (x, 0)) == REG
&& GET_CODE (XEXP (x, 1)) == CONST_INT
&& ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
- >= 0x10000 - extra)
- && !PAIRED_VECTOR_MODE (mode))
+ >= 0x10000 - extra))
{
HOST_WIDE_INT high_int, low_int;
rtx sum;
@@ -8789,33 +8590,6 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
return gen_rtx_PLUS (Pmode, XEXP (x, 0),
force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
}
- else if (PAIRED_VECTOR_MODE (mode))
- {
- if (mode == DImode)
- return x;
- /* We accept [reg + reg]. */
-
- if (GET_CODE (x) == PLUS)
- {
- rtx op1 = XEXP (x, 0);
- rtx op2 = XEXP (x, 1);
- rtx y;
-
- op1 = force_reg (Pmode, op1);
- op2 = force_reg (Pmode, op2);
-
- /* We can't always do [reg + reg] for these, because [reg +
- reg + offset] is not a legitimate addressing mode. */
- y = gen_rtx_PLUS (Pmode, op1, op2);
-
- if ((GET_MODE_SIZE (mode) > 8 || mode == DDmode) && REG_P (op2))
- return force_reg (Pmode, y);
- else
- return y;
- }
-
- return force_reg (Pmode, x);
- }
else if ((TARGET_ELF
#if TARGET_MACHO
|| !MACHO_DYNAMIC_NO_PIC_P
@@ -9548,7 +9322,6 @@ rs6000_legitimize_reload_address (rtx x, machine_mode mode,
&& INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
&& CONST_INT_P (XEXP (x, 1))
&& reg_offset_p
- && !PAIRED_VECTOR_MODE (mode)
&& (quad_offset_p || !VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode)))
{
HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
@@ -9589,7 +9362,6 @@ rs6000_legitimize_reload_address (rtx x, machine_mode mode,
&& reg_offset_p
&& !quad_offset_p
&& (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode))
- && !PAIRED_VECTOR_MODE (mode)
#if TARGET_MACHO
&& DEFAULT_ABI == ABI_DARWIN
&& (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
@@ -10745,8 +10517,6 @@ rs6000_emit_move (rtx dest, rtx source, machine_mode mode)
case E_V8HImode:
case E_V4SFmode:
case E_V4SImode:
- case E_V2SFmode:
- case E_V2SImode:
case E_V2DFmode:
case E_V2DImode:
case E_V1TImode:
@@ -11386,8 +11156,7 @@ init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
== long_double_type_node))))
rs6000_passes_long_double = true;
}
- if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode)
- || PAIRED_VECTOR_MODE (return_mode))
+ if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode))
rs6000_passes_vector = true;
}
}
@@ -11560,10 +11329,9 @@ rs6000_function_arg_boundary (machine_mode mode, const_tree type)
return 64;
else if (FLOAT128_VECTOR_P (mode))
return 128;
- else if (PAIRED_VECTOR_MODE (mode)
- || (type && TREE_CODE (type) == VECTOR_TYPE
- && int_size_in_bytes (type) >= 8
- && int_size_in_bytes (type) < 16))
+ else if (type && TREE_CODE (type) == VECTOR_TYPE
+ && int_size_in_bytes (type) >= 8
+ && int_size_in_bytes (type) < 16)
return 64;
else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
|| (type && TREE_CODE (type) == VECTOR_TYPE
@@ -11839,10 +11607,7 @@ rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode,
&& TYPE_MAIN_VARIANT (type) == long_double_type_node)))
rs6000_passes_long_double = true;
}
- if ((named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
- || (PAIRED_VECTOR_MODE (mode)
- && !cum->stdarg
- && cum->sysv_gregno <= GP_ARG_MAX_REG))
+ if (named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
rs6000_passes_vector = true;
}
#endif
@@ -13629,7 +13394,6 @@ def_builtin (const char *name, tree type, enum rs6000_builtins code)
#undef RS6000_BUILTIN_D
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
#undef RS6000_BUILTIN_X
#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
@@ -13642,7 +13406,6 @@ def_builtin (const char *name, tree type, enum rs6000_builtins code)
#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
static const struct builtin_description bdesc_3arg[] =
@@ -13660,7 +13423,6 @@ static const struct builtin_description bdesc_3arg[] =
#undef RS6000_BUILTIN_D
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
#undef RS6000_BUILTIN_X
#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
@@ -13673,7 +13435,6 @@ static const struct builtin_description bdesc_3arg[] =
#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
static const struct builtin_description bdesc_dst[] =
@@ -13691,7 +13452,6 @@ static const struct builtin_description bdesc_dst[] =
#undef RS6000_BUILTIN_D
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
#undef RS6000_BUILTIN_X
#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
@@ -13704,7 +13464,6 @@ static const struct builtin_description bdesc_dst[] =
#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
static const struct builtin_description bdesc_2arg[] =
@@ -13720,7 +13479,6 @@ static const struct builtin_description bdesc_2arg[] =
#undef RS6000_BUILTIN_D
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
#undef RS6000_BUILTIN_X
#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
@@ -13733,7 +13491,6 @@ static const struct builtin_description bdesc_2arg[] =
#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
{ MASK, ICODE, NAME, ENUM },
-#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
/* AltiVec predicates. */
@@ -13743,36 +13500,6 @@ static const struct builtin_description bdesc_altivec_preds[] =
#include "rs6000-builtin.def"
};
-/* PAIRED predicates. */
-#undef RS6000_BUILTIN_0
-#undef RS6000_BUILTIN_1
-#undef RS6000_BUILTIN_2
-#undef RS6000_BUILTIN_3
-#undef RS6000_BUILTIN_A
-#undef RS6000_BUILTIN_D
-#undef RS6000_BUILTIN_H
-#undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
-#undef RS6000_BUILTIN_X
-
-#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
- { MASK, ICODE, NAME, ENUM },
-
-#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
-
-static const struct builtin_description bdesc_paired_preds[] =
-{
-#include "rs6000-builtin.def"
-};
-
/* ABS* operations. */
#undef RS6000_BUILTIN_0
@@ -13783,7 +13510,6 @@ static const struct builtin_description bdesc_paired_preds[] =
#undef RS6000_BUILTIN_D
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
#undef RS6000_BUILTIN_X
#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
@@ -13796,7 +13522,6 @@ static const struct builtin_description bdesc_paired_preds[] =
#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
static const struct builtin_description bdesc_abs[] =
@@ -13815,7 +13540,6 @@ static const struct builtin_description bdesc_abs[] =
#undef RS6000_BUILTIN_D
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
#undef RS6000_BUILTIN_X
#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
@@ -13828,7 +13552,6 @@ static const struct builtin_description bdesc_abs[] =
#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
static const struct builtin_description bdesc_1arg[] =
@@ -13846,7 +13569,6 @@ static const struct builtin_description bdesc_1arg[] =
#undef RS6000_BUILTIN_D
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
#undef RS6000_BUILTIN_X
#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
@@ -13859,7 +13581,6 @@ static const struct builtin_description bdesc_1arg[] =
#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
static const struct builtin_description bdesc_0arg[] =
@@ -13876,7 +13597,6 @@ static const struct builtin_description bdesc_0arg[] =
#undef RS6000_BUILTIN_D
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
#undef RS6000_BUILTIN_X
#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
@@ -13889,7 +13609,6 @@ static const struct builtin_description bdesc_0arg[] =
{ MASK, ICODE, NAME, ENUM },
#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
static const struct builtin_description bdesc_htm[] =
@@ -13905,7 +13624,6 @@ static const struct builtin_description bdesc_htm[] =
#undef RS6000_BUILTIN_D
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
/* Return true if a builtin function is overloaded. */
bool
@@ -14252,52 +13970,6 @@ altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
return target;
}
-static rtx
-paired_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
-{
- rtx pat, addr;
- tree arg0 = CALL_EXPR_ARG (exp, 0);
- tree arg1 = CALL_EXPR_ARG (exp, 1);
- machine_mode tmode = insn_data[icode].operand[0].mode;
- machine_mode mode0 = Pmode;
- machine_mode mode1 = Pmode;
- rtx op0 = expand_normal (arg0);
- rtx op1 = expand_normal (arg1);
-
- if (icode == CODE_FOR_nothing)
- /* Builtin not supported on this processor. */
- return 0;
-
- /* If we got invalid arguments bail out before generating bad rtl. */
- if (arg0 == error_mark_node || arg1 == error_mark_node)
- return const0_rtx;
-
- if (target == 0
- || GET_MODE (target) != tmode
- || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
- target = gen_reg_rtx (tmode);
-
- op1 = copy_to_mode_reg (mode1, op1);
-
- if (op0 == const0_rtx)
- {
- addr = gen_rtx_MEM (tmode, op1);
- }
- else
- {
- op0 = copy_to_mode_reg (mode0, op0);
- addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
- }
-
- pat = GEN_FCN (icode) (target, addr);
-
- if (! pat)
- return 0;
- emit_insn (pat);
-
- return target;
-}
-
/* Return a constant vector for use as a little-endian permute control vector
to reverse the order of elements of the given vector mode. */
static rtx
@@ -14515,47 +14187,6 @@ altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
}
static rtx
-paired_expand_stv_builtin (enum insn_code icode, tree exp)
-{
- tree arg0 = CALL_EXPR_ARG (exp, 0);
- tree arg1 = CALL_EXPR_ARG (exp, 1);
- tree arg2 = CALL_EXPR_ARG (exp, 2);
- rtx op0 = expand_normal (arg0);
- rtx op1 = expand_normal (arg1);
- rtx op2 = expand_normal (arg2);
- rtx pat, addr;
- machine_mode tmode = insn_data[icode].operand[0].mode;
- machine_mode mode1 = Pmode;
- machine_mode mode2 = Pmode;
-
- /* Invalid arguments. Bail before doing anything stoopid! */
- if (arg0 == error_mark_node
- || arg1 == error_mark_node
- || arg2 == error_mark_node)
- return const0_rtx;
-
- if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
- op0 = copy_to_mode_reg (tmode, op0);
-
- op2 = copy_to_mode_reg (mode2, op2);
-
- if (op1 == const0_rtx)
- {
- addr = gen_rtx_MEM (tmode, op2);
- }
- else
- {
- op1 = copy_to_mode_reg (mode1, op1);
- addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
- }
-
- pat = GEN_FCN (icode) (addr, op0);
- if (pat)
- emit_insn (pat);
- return NULL_RTX;
-}
-
-static rtx
altivec_expand_stxvl_builtin (enum insn_code icode, tree exp)
{
rtx pat;
@@ -15182,10 +14813,7 @@ rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
op2 = copy_to_mode_reg (mode2, op2);
- if (TARGET_PAIRED_FLOAT && icode == CODE_FOR_selv2sf4)
- pat = GEN_FCN (icode) (target, op0, op1, op2, CONST0_RTX (SFmode));
- else
- pat = GEN_FCN (icode) (target, op0, op1, op2);
+ pat = GEN_FCN (icode) (target, op0, op1, op2);
if (! pat)
return 0;
emit_insn (pat);
@@ -15798,113 +15426,6 @@ altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
return NULL_RTX;
}
-/* Expand the builtin in EXP and store the result in TARGET. Store
- true in *EXPANDEDP if we found a builtin to expand. */
-static rtx
-paired_expand_builtin (tree exp, rtx target, bool * expandedp)
-{
- tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
- enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
- const struct builtin_description *d;
- size_t i;
-
- *expandedp = true;
-
- switch (fcode)
- {
- case PAIRED_BUILTIN_STX:
- return paired_expand_stv_builtin (CODE_FOR_paired_stx, exp);
- case PAIRED_BUILTIN_LX:
- return paired_expand_lv_builtin (CODE_FOR_paired_lx, exp, target);
- default:
- break;
- /* Fall through. */
- }
-
- /* Expand the paired predicates. */
- d = bdesc_paired_preds;
- for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); i++, d++)
- if (d->code == fcode)
- return paired_expand_predicate_builtin (d->icode, exp, target);
-
- *expandedp = false;
- return NULL_RTX;
-}
-
-static rtx
-paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
-{
- rtx pat, scratch, tmp;
- tree form = CALL_EXPR_ARG (exp, 0);
- tree arg0 = CALL_EXPR_ARG (exp, 1);
- tree arg1 = CALL_EXPR_ARG (exp, 2);
- rtx op0 = expand_normal (arg0);
- rtx op1 = expand_normal (arg1);
- machine_mode mode0 = insn_data[icode].operand[1].mode;
- machine_mode mode1 = insn_data[icode].operand[2].mode;
- int form_int;
- enum rtx_code code;
-
- if (TREE_CODE (form) != INTEGER_CST)
- {
- error ("argument 1 of %s must be a constant",
- "__builtin_paired_predicate");
- return const0_rtx;
- }
- else
- form_int = TREE_INT_CST_LOW (form);
-
- gcc_assert (mode0 == mode1);
-
- if (arg0 == error_mark_node || arg1 == error_mark_node)
- return const0_rtx;
-
- if (target == 0
- || GET_MODE (target) != SImode
- || !(*insn_data[icode].operand[0].predicate) (target, SImode))
- target = gen_reg_rtx (SImode);
- if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
- op0 = copy_to_mode_reg (mode0, op0);
- if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
- op1 = copy_to_mode_reg (mode1, op1);
-
- scratch = gen_reg_rtx (CCFPmode);
-
- pat = GEN_FCN (icode) (scratch, op0, op1);
- if (!pat)
- return const0_rtx;
-
- emit_insn (pat);
-
- switch (form_int)
- {
- /* LT bit. */
- case 0:
- code = LT;
- break;
- /* GT bit. */
- case 1:
- code = GT;
- break;
- /* EQ bit. */
- case 2:
- code = EQ;
- break;
- /* UN bit. */
- case 3:
- emit_insn (gen_move_from_CR_ov_bit (target, scratch));
- return target;
- default:
- error ("argument 1 of %qs is out of range",
- "__builtin_paired_predicate");
- return const0_rtx;
- }
-
- tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
- emit_move_insn (target, tmp);
- return target;
-}
-
/* Check whether a builtin function is supported in this target
configuration. */
bool
@@ -15936,8 +15457,6 @@ rs6000_invalid_builtin (enum rs6000_builtins fncode)
error ("builtin function %qs requires the %qs option", name, "-mhtm");
else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
error ("builtin function %qs requires the %qs option", name, "-maltivec");
- else if ((fnmask & RS6000_BTM_PAIRED) != 0)
- error ("builtin function %qs requires the %qs option", name, "-mpaired");
else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
== (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
error ("builtin function %qs requires the %qs and %qs options",
@@ -16856,13 +16375,6 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
if (success)
return ret;
}
- if (TARGET_PAIRED_FLOAT)
- {
- ret = paired_expand_builtin (exp, target, &success);
-
- if (success)
- return ret;
- }
if (TARGET_HTM)
{
ret = htm_expand_builtin (exp, target, &success);
@@ -16929,13 +16441,10 @@ rs6000_init_builtins (void)
machine_mode mode;
if (TARGET_DEBUG_BUILTIN)
- fprintf (stderr, "rs6000_init_builtins%s%s%s\n",
- (TARGET_PAIRED_FLOAT) ? ", paired" : "",
+ fprintf (stderr, "rs6000_init_builtins%s%s\n",
(TARGET_ALTIVEC) ? ", altivec" : "",
(TARGET_VSX) ? ", vsx" : "");
- V2SI_type_node = build_vector_type (intSI_type_node, 2);
- V2SF_type_node = build_vector_type (float_type_node, 2);
V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64 ? "__vector long"
: "__vector long long",
intDI_type_node, 2);
@@ -16959,9 +16468,6 @@ rs6000_init_builtins (void)
: "__vector unsigned long long",
unsigned_intDI_type_node, 2);
- opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
- opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
- opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
const_str_type_node
@@ -17069,8 +16575,6 @@ rs6000_init_builtins (void)
builtin_mode_to_type[TDmode][0] = dfloat128_type_node;
builtin_mode_to_type[V1TImode][0] = V1TI_type_node;
builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node;
- builtin_mode_to_type[V2SImode][0] = V2SI_type_node;
- builtin_mode_to_type[V2SFmode][0] = V2SF_type_node;
builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
@@ -17107,19 +16611,15 @@ rs6000_init_builtins (void)
pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel",
pixel_type_node, 8);
- /* Paired builtins are only available if you build a compiler with the
- appropriate options, so only create those builtins with the appropriate
- compiler option. Create Altivec and VSX builtins on machines with at
- least the general purpose extensions (970 and newer) to allow the use of
+ /* Create Altivec and VSX builtins on machines with at least the
+ general purpose extensions (970 and newer) to allow the use of
the target attribute. */
- if (TARGET_PAIRED_FLOAT)
- paired_init_builtins ();
if (TARGET_EXTRA_BUILTINS)
altivec_init_builtins ();
if (TARGET_HTM)
htm_init_builtins ();
- if (TARGET_EXTRA_BUILTINS || TARGET_PAIRED_FLOAT)
+ if (TARGET_EXTRA_BUILTINS)
rs6000_common_init_builtins ();
ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
@@ -17204,78 +16704,6 @@ rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
}
static void
-paired_init_builtins (void)
-{
- const struct builtin_description *d;
- size_t i;
- HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
-
- tree int_ftype_int_v2sf_v2sf
- = build_function_type_list (integer_type_node,
- integer_type_node,
- V2SF_type_node,
- V2SF_type_node,
- NULL_TREE);
- tree pcfloat_type_node =
- build_pointer_type (build_qualified_type
- (float_type_node, TYPE_QUAL_CONST));
-
- tree v2sf_ftype_long_pcfloat = build_function_type_list (V2SF_type_node,
- long_integer_type_node,
- pcfloat_type_node,
- NULL_TREE);
- tree void_ftype_v2sf_long_pcfloat =
- build_function_type_list (void_type_node,
- V2SF_type_node,
- long_integer_type_node,
- pcfloat_type_node,
- NULL_TREE);
-
-
- def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat,
- PAIRED_BUILTIN_LX);
-
-
- def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat,
- PAIRED_BUILTIN_STX);
-
- /* Predicates. */
- d = bdesc_paired_preds;
- for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); ++i, d++)
- {
- tree type;
- HOST_WIDE_INT mask = d->mask;
-
- if ((mask & builtin_mask) != mask)
- {
- if (TARGET_DEBUG_BUILTIN)
- fprintf (stderr, "paired_init_builtins, skip predicate %s\n",
- d->name);
- continue;
- }
-
- /* Cannot define builtin if the instruction is disabled. */
- gcc_assert (d->icode != CODE_FOR_nothing);
-
- if (TARGET_DEBUG_BUILTIN)
- fprintf (stderr, "paired pred #%d, insn = %s [%d], mode = %s\n",
- (int)i, get_insn_name (d->icode), (int)d->icode,
- GET_MODE_NAME (insn_data[d->icode].operand[1].mode));
-
- switch (insn_data[d->icode].operand[1].mode)
- {
- case E_V2SFmode:
- type = int_ftype_int_v2sf_v2sf;
- break;
- default:
- gcc_unreachable ();
- }
-
- def_builtin (d->name, type, d->code);
- }
-}
-
-static void
altivec_init_builtins (void)
{
const struct builtin_description *d;
@@ -18260,23 +17688,11 @@ rs6000_common_init_builtins (void)
tree opaque_ftype_opaque = NULL_TREE;
tree opaque_ftype_opaque_opaque = NULL_TREE;
tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
- tree v2si_ftype = NULL_TREE;
- tree v2si_ftype_qi = NULL_TREE;
- tree v2si_ftype_v2si_qi = NULL_TREE;
- tree v2si_ftype_int_qi = NULL_TREE;
HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
- if (!TARGET_PAIRED_FLOAT)
- {
- builtin_mode_to_type[V2SImode][0] = opaque_V2SI_type_node;
- builtin_mode_to_type[V2SFmode][0] = opaque_V2SF_type_node;
- }
-
- /* Paired builtins are only available if you build a compiler with the
- appropriate options, so only create those builtins with the appropriate
- compiler option. Create Altivec and VSX builtins on machines with at
- least the general purpose extensions (970 and newer) to allow the use of
- the target attribute.. */
+ /* Create Altivec and VSX builtins on machines with at least the
+ general purpose extensions (970 and newer) to allow the use of
+ the target attribute. */
if (TARGET_EXTRA_BUILTINS)
builtin_mask |= RS6000_BTM_COMMON;
@@ -18385,30 +17801,8 @@ rs6000_common_init_builtins (void)
mode1 = insn_data[icode].operand[1].mode;
mode2 = insn_data[icode].operand[2].mode;
- if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
- {
- if (! (type = v2si_ftype_v2si_qi))
- type = v2si_ftype_v2si_qi
- = build_function_type_list (opaque_V2SI_type_node,
- opaque_V2SI_type_node,
- char_type_node,
- NULL_TREE);
- }
-
- else if (mode0 == V2SImode && GET_MODE_CLASS (mode1) == MODE_INT
- && mode2 == QImode)
- {
- if (! (type = v2si_ftype_int_qi))
- type = v2si_ftype_int_qi
- = build_function_type_list (opaque_V2SI_type_node,
- integer_type_node,
- char_type_node,
- NULL_TREE);
- }
-
- else
- type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
- d->code, d->name);
+ type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
+ d->code, d->name);
}
def_builtin (d->name, type, d->code);
@@ -18461,18 +17855,8 @@ rs6000_common_init_builtins (void)
mode0 = insn_data[icode].operand[0].mode;
mode1 = insn_data[icode].operand[1].mode;
- if (mode0 == V2SImode && mode1 == QImode)
- {
- if (! (type = v2si_ftype_qi))
- type = v2si_ftype_qi
- = build_function_type_list (opaque_V2SI_type_node,
- char_type_node,
- NULL_TREE);
- }
-
- else
- type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
- d->code, d->name);
+ type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
+ d->code, d->name);
}
def_builtin (d->name, type, d->code);
@@ -18518,20 +17902,8 @@ rs6000_common_init_builtins (void)
continue;
}
mode0 = insn_data[icode].operand[0].mode;
- if (mode0 == V2SImode)
- {
- /* code for paired single */
- if (! (type = v2si_ftype))
- {
- v2si_ftype
- = build_function_type_list (opaque_V2SI_type_node,
- NULL_TREE);
- type = v2si_ftype;
- }
- }
- else
- type = builtin_function_type (mode0, VOIDmode, VOIDmode, VOIDmode,
- d->code, d->name);
+ type = builtin_function_type (mode0, VOIDmode, VOIDmode, VOIDmode,
+ d->code, d->name);
}
def_builtin (d->name, type, d->code);
}
@@ -35954,7 +35326,7 @@ altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1,
return false;
}
-/* Expand a Paired Single or VSX Permute Doubleword constant permutation.
+/* Expand a VSX Permute Doubleword constant permutation.
Return true if we match an efficient implementation. */
static bool
@@ -36020,9 +35392,7 @@ rs6000_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0,
return true;
/* Check for ps_merge* or xxpermdi insns. */
- if ((vmode == V2SFmode && TARGET_PAIRED_FLOAT)
- || ((vmode == V2DFmode || vmode == V2DImode)
- && VECTOR_MEM_VSX_P (vmode)))
+ if ((vmode == V2DFmode || vmode == V2DImode) && VECTOR_MEM_VSX_P (vmode))
{
if (testing_p)
{
@@ -36477,14 +35847,10 @@ rs6000_scalar_mode_supported_p (scalar_mode mode)
static bool
rs6000_vector_mode_supported_p (machine_mode mode)
{
-
- if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (mode))
- return true;
-
/* There is no vector form for IEEE 128-bit. If we return true for IEEE
128-bit, the compiler might try to widen IEEE 128-bit to IBM
double-double. */
- else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) && !FLOAT128_IEEE_P (mode))
+ if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) && !FLOAT128_IEEE_P (mode))
return true;
else
@@ -36678,7 +36044,6 @@ static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
{
{ "altivec", RS6000_BTM_ALTIVEC, false, false },
{ "vsx", RS6000_BTM_VSX, false, false },
- { "paired", RS6000_BTM_PAIRED, false, false },
{ "fre", RS6000_BTM_FRE, false, false },
{ "fres", RS6000_BTM_FRES, false, false },
{ "frsqrte", RS6000_BTM_FRSQRTE, false, false },
@@ -36715,9 +36080,6 @@ static struct rs6000_opt_var const rs6000_opt_vars[] =
{ "avoid-indexed-addresses",
offsetof (struct gcc_options, x_TARGET_AVOID_XFORM),
offsetof (struct cl_target_option, x_TARGET_AVOID_XFORM) },
- { "paired",
- offsetof (struct gcc_options, x_rs6000_paired_float),
- offsetof (struct cl_target_option, x_rs6000_paired_float), },
{ "longcall",
offsetof (struct gcc_options, x_rs6000_default_long_calls),
offsetof (struct cl_target_option, x_rs6000_default_long_calls), },
@@ -67,10 +67,6 @@
#define PPC405_ERRATUM77 0
#endif
-#ifndef TARGET_PAIRED_FLOAT
-#define TARGET_PAIRED_FLOAT 0
-#endif
-
#ifdef HAVE_AS_POPCNTB
#define ASM_CPU_POWER5_SPEC "-mpower5"
#else
@@ -695,19 +691,16 @@ extern int rs6000_vector_align[];
/* For power systems, we want to enable Altivec and VSX builtins even if the
user did not use -maltivec or -mvsx to allow the builtins to be used inside
of #pragma GCC target or the target attribute to change the code level for a
- given system. The Paired builtins are only enabled if you configure the
- compiler for those builtins, and those machines don't support altivec or
- VSX. */
+ given system. */
-#define TARGET_EXTRA_BUILTINS (!TARGET_PAIRED_FLOAT \
- && ((TARGET_POWERPC64 \
- || TARGET_PPC_GPOPT /* 970/power4 */ \
- || TARGET_POPCNTB /* ISA 2.02 */ \
- || TARGET_CMPB /* ISA 2.05 */ \
- || TARGET_POPCNTD /* ISA 2.06 */ \
- || TARGET_ALTIVEC \
- || TARGET_VSX \
- || TARGET_HARD_FLOAT)))
+#define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \
+ || TARGET_PPC_GPOPT /* 970/power4 */ \
+ || TARGET_POPCNTB /* ISA 2.02 */ \
+ || TARGET_CMPB /* ISA 2.05 */ \
+ || TARGET_POPCNTD /* ISA 2.06 */ \
+ || TARGET_ALTIVEC \
+ || TARGET_VSX \
+ || TARGET_HARD_FLOAT)
/* E500 cores only support plain "sync", not lwsync. */
#define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \
@@ -863,7 +856,6 @@ extern unsigned char rs6000_recip_bits[];
#define UNITS_PER_FP_WORD 8
#define UNITS_PER_ALTIVEC_WORD 16
#define UNITS_PER_VSX_WORD 16
-#define UNITS_PER_PAIRED_WORD 8
/* Type used for ptrdiff_t, as a string used in a declaration. */
#define PTRDIFF_TYPE "int"
@@ -1169,9 +1161,6 @@ enum data_align { align_abi, align_opt, align_both };
#define INT_REGNO_P(N) \
((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
-/* PAIRED SIMD registers are just the FPRs. */
-#define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
-
/* True if register is the CA register. */
#define CA_REGNO_P(N) ((N) == CA_REGNO)
@@ -1232,9 +1221,6 @@ enum data_align { align_abi, align_opt, align_both };
(ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \
|| (MODE) == V2DImode || (MODE) == V1TImode)
-#define PAIRED_VECTOR_MODE(MODE) \
- ((MODE) == V2SFmode)
-
/* Post-reload, we can't use any new AltiVec registers, as we already
emitted the vrsave mask. */
@@ -2484,8 +2470,8 @@ extern int frame_pointer_needed;
#define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */
/* Builtin targets. For now, we reuse the masks for those options that are in
- target flags, and pick two random bits for paired and ldbl128, which
- aren't in target_flags. */
+ target flags, and pick a random bit for ldbl128, which isn't in
+ target_flags. */
#define RS6000_BTM_ALWAYS 0 /* Always enabled. */
#define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */
#define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */
@@ -2495,7 +2481,6 @@ extern int frame_pointer_needed;
#define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */
#define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */
#define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */
-#define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */
#define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */
#define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */
#define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */
@@ -2541,7 +2526,6 @@ extern int frame_pointer_needed;
#undef RS6000_BUILTIN_D
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
#undef RS6000_BUILTIN_X
#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
@@ -2552,7 +2536,6 @@ extern int frame_pointer_needed;
#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
-#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
enum rs6000_builtins
@@ -2570,20 +2553,14 @@ enum rs6000_builtins
#undef RS6000_BUILTIN_D
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
#undef RS6000_BUILTIN_X
enum rs6000_builtin_type_index
{
RS6000_BTI_NOT_OPAQUE,
- RS6000_BTI_opaque_V2SI,
- RS6000_BTI_opaque_V2SF,
- RS6000_BTI_opaque_p_V2SI,
RS6000_BTI_opaque_V4SI,
RS6000_BTI_V16QI, /* __vector signed char */
RS6000_BTI_V1TI,
- RS6000_BTI_V2SI,
- RS6000_BTI_V2SF,
RS6000_BTI_V2DI,
RS6000_BTI_V2DF,
RS6000_BTI_V4HI,
@@ -2638,16 +2615,11 @@ enum rs6000_builtin_type_index
};
-#define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI])
-#define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF])
-#define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])
#define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
#define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
#define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI])
#define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI])
#define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF])
-#define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])
-#define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF])
#define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
#define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
#define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
@@ -394,7 +394,6 @@ (define_mode_iterator FMA_F [
(SF "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT")
(DF "(TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
|| VECTOR_UNIT_VSX_P (DFmode)")
- (V2SF "TARGET_PAIRED_FLOAT")
(V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
(V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
(KF "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (KFmode)")
@@ -11663,16 +11662,6 @@ (define_insn ""
(const_string "mfcr")))
(set_attr "length" "8")])
-;; Same as above, but get the OV/ORDERED bit.
-(define_insn "move_from_CR_ov_bit"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")]
- UNSPEC_MV_CR_OV))]
- "TARGET_PAIRED_FLOAT"
- "mfcr %0\;rlwinm %0,%0,%t1,1"
- [(set_attr "type" "mfcr")
- (set_attr "length" "8")])
-
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(match_operator:DI 1 "scc_comparison_operator"
@@ -14572,6 +14561,5 @@ (define_insn "*cmp<mode>_hw"
(include "vsx.md")
(include "altivec.md")
(include "dfp.md")
-(include "paired.md")
(include "crypto.md")
(include "htm.md")
@@ -357,10 +357,6 @@ misel=yes
Target RejectNegative Alias(misel) Warn(%<-misel=yes%> is deprecated; use %<-misel%> instead)
Deprecated option. Use -misel instead.
-mpaired
-Target Var(rs6000_paired_float) Save
-Generate PPC750CL paired-single instructions.
-
mdebug=
Target RejectNegative Joined
-mdebug= Enable debug output.
@@ -72,5 +72,4 @@ MD_INCLUDES = $(srcdir)/config/rs6000/rs64.md \
$(srcdir)/config/rs6000/altivec.md \
$(srcdir)/config/rs6000/crypto.md \
$(srcdir)/config/rs6000/htm.md \
- $(srcdir)/config/rs6000/dfp.md \
- $(srcdir)/config/rs6000/paired.md
+ $(srcdir)/config/rs6000/dfp.md
@@ -1088,7 +1088,6 @@ See RS/6000 and PowerPC Options.
-mstring-compare-inline-limit=@var{num} @gol
-misel -mno-isel @gol
-misel=yes -misel=no @gol
--mpaired @gol
-mvrsave -mno-vrsave @gol
-mmulhw -mno-mulhw @gol
-mdlmzb -mno-dlmzb @gol
@@ -23482,13 +23481,6 @@ This switch enables or disables the generation of ISEL instructions.
This switch has been deprecated. Use @option{-misel} and
@option{-mno-isel} instead.
-@item -mpaired
-@itemx -mno-paired
-@opindex mpaired
-@opindex mno-paired
-This switch enables or disables the generation of PAIRED simd
-instructions.
-
@item -mvsx
@itemx -mno-vsx
@opindex mvsx
This removes paired single (used on the 750CL and friends). It was deprecated in GCC 8. Removing it means we only have one vector model to deal with (VMX+VSX, 16-byte vectors). Tested on powerpc64-linux {-m32,-m64} and on powerpc64le-linux. I plan to commit this later this week. Segher 2018-04-30 Segher Boessenkool <segher@kernel.crashing.org> * config.gcc (powerpc*-*-*): Remove paired.h. Unsupport the powerpc*-*-linux*paired* target. * config/rs6000/750cl.h: Delete. * config/rs6000/paired.h: Delete. * config/rs6000/paired.md: Delete. * config/rs6000/predicates.md (easy_vector_constant): Remove paired float support. * config/rs6000/rs6000-builtin.def: Remove paired float support. * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Update comment. Remove paired float support. * config/rs6000/rs6000-modes.def: Remove V2SF and V2SI. * config/rs6000/rs6000-opts.h (enum rs6000_vector): Delete VECTOR_PAIRED. * config/rs6000/rs6000-protos.h (paired_expand_vector_init, paired_emit_vector_cond_expr, paired_expand_vector_move): Delete declarations. * config/rs6000/rs6000.c: Remove paired float support. (paired_expand_vector_init, paired_expand_vector_move, paired_emit_vector_compare, paired_emit_vector_cond_expr, (paired_expand_lv_builtin, paired_expand_stv_builtin, paired_expand_builtin, paired_expand_predicate_builtin, paired_init_builtins): Delete. * config/rs6000/rs6000.h: Remove paired float support. * config/rs6000/rs6000.md: Remove paired float support. (move_from_CR_ov_bit): Delete. * config/rs6000/rs6000.opt (mpaired): Delete. * config/rs6000/t-rs6000: Remove paired.md from MD_INCLUDES. * doc/invoke.texi (RS/6000 and PowerPC Options): Delete -mpaired. --- gcc/config.gcc | 7 +- gcc/config/rs6000/750cl.h | 30 -- gcc/config/rs6000/paired.h | 75 ---- gcc/config/rs6000/paired.md | 492 ------------------------ gcc/config/rs6000/predicates.md | 5 - gcc/config/rs6000/rs6000-builtin.def | 84 ----- gcc/config/rs6000/rs6000-c.c | 13 +- gcc/config/rs6000/rs6000-modes.def | 4 - gcc/config/rs6000/rs6000-opts.h | 1 - gcc/config/rs6000/rs6000-protos.h | 4 - gcc/config/rs6000/rs6000.c | 698 ++--------------------------------- gcc/config/rs6000/rs6000.h | 50 +-- gcc/config/rs6000/rs6000.md | 12 - gcc/config/rs6000/rs6000.opt | 4 - gcc/config/rs6000/t-rs6000 | 3 +- gcc/doc/invoke.texi | 8 - 16 files changed, 47 insertions(+), 1443 deletions(-) delete mode 100644 gcc/config/rs6000/750cl.h delete mode 100644 gcc/config/rs6000/paired.h delete mode 100644 gcc/config/rs6000/paired.md