diff mbox

[4/n,i386] : Merge SSE and AVX patterns using "enable" attribute.

Message ID BANLkTinCAtAQHV-XH88P0NgESvGbdUoWMA@mail.gmail.com
State New
Headers show

Commit Message

Uros Bizjak April 11, 2011, 4:09 p.m. UTC 
Hello!

Attached patch merges SSE and AVX patterns in "Parallel integral
arithmetic" and "Parallel integral comparisons" sections of sse.md.

2011-04-11  Uros Bizjak  <ubizjak@gmail.com>

	* config/i386/sse.md (VI_128): New mode iterator.
	(VI12_128): Rename from SSEMODE12.
	(VI14_128): Rename from SSEMODE14.
	(VI124_128): New mode iterator.
	(VI24_128): Rename from SSEMODE248.
	(VI248_128): Rename from SSEMODE248.
	(SSEMODE124C8): Remove.
	(*<plusminus_insn><mode>3): Merge with *avx_<plusminus_insn><mode>3.
	(*sse2_<plusminus_insn><mode>3): Merge with
	*avx_<plusminus_insn><mode>3.
	(*mulv8hi3): Merge with *avx_mulv8hi3.
	(*<s>mulv8hi3_highpart): Merge with *avx_<s>mulv8hi3_highpart.
	(*sse2_umulv2siv2di3): Merge with *avx_umulv2siv2di3.
	(*sse2_pmaddwd): Merge with *avx_pmaddwd.
	(*sse4_1_mulv4si3): Merge with *avx_mulv4si3.
	(ashr<mode>3): Merge with *avx_ashr<mode>3.
	(lshr<mode>3): Merge with *avx_lshr<mode>3.
	(ashl<mode>3): Merge with *avx_ashl<mode>3.
	(sse2_ashlv1ti3): Merge with *avx_ashlv1ti3.
	(sse2_lshrv1ti3): Merge with *avx_lshrv1ti3.
	(*sse4_1_<smaxmin:code><mode>3): Merge with *avx_<smaxmin:code><mode>3.
	(*<smaxmin:code>v8hi3): Ditto.
	(*sse4_1_<umaxmin:code><mode>3): Merge with *avx_<umaxmin:code><mode>3.
	(*<smaxmin:code>v16qi3): Ditto.
	(*sse4_1_eqv2di3): Merge with *avx_eq<mode>3.
	(*sse2_eq<mode>3): Ditto.
	(*sse4_2_eqv2di3): Merge with *avx_gt<mode>3.
	(*sse2_gt<mode>3): Ditto.
	(vcondv2di): Split out of vcond<mode>.
	(vconduv2di): Split out of vcondu<mode>.

Patch was bootstrapped and regression tested on x86_64-pc-linux-gnu
{,-m32} AVX target.

Committed to mainline SVN.

Uros.
diff mbox

Patch

Index: config/i386/sse.md
===================================================================
--- config/i386/sse.md	(revision 172252)
+++ config/i386/sse.md	(working copy)
@@ -36,8 +36,17 @@ 
 (define_mode_iterator VF_128
   [(V4SF "TARGET_SSE") (V2DF "TARGET_SSE2")])
 
+;; All 128bit vector integer modes
+(define_mode_iterator VI_128 [V16QI V8HI V4SI V2DI])
 
+;; Random 128bit vector integer mode combinations
+(define_mode_iterator VI12_128 [V16QI V8HI])
+(define_mode_iterator VI14_128 [V16QI V4SI])
+(define_mode_iterator VI124_128 [V16QI V8HI V4SI])
+(define_mode_iterator VI24_128 [V8HI V4SI])
+(define_mode_iterator VI248_128 [V8HI V4SI V2DI])
 
+
 ;; Instruction suffix for sign and zero extensions.
 (define_code_attr extsuffix [(sign_extend "sx") (zero_extend "zx")])
 
@@ -67,11 +76,7 @@ 
   [V16QI V8HI V4SI V2DI V1TI V4SF V2DF V32QI V16HI V8SI V4DI V8SF V4DF])
 
 ;; Mix-n-match
-(define_mode_iterator SSEMODE12 [V16QI V8HI])
-(define_mode_iterator SSEMODE24 [V8HI V4SI])
-(define_mode_iterator SSEMODE14 [V16QI V4SI])
 (define_mode_iterator SSEMODE124 [V16QI V8HI V4SI])
-(define_mode_iterator SSEMODE248 [V8HI V4SI V2DI])
 (define_mode_iterator SSEMODE1248 [V16QI V8HI V4SI V2DI])
 (define_mode_iterator SSEMODEF2P [V4SF V2DF])
 
@@ -91,10 +96,6 @@ 
 (define_mode_iterator SSEMODE4S [V4SF V4SI])
 (define_mode_iterator SSEMODE2D [V2DF V2DI])
 
-;; Modes handled by integer vcond pattern
-(define_mode_iterator SSEMODE124C8 [V16QI V8HI V4SI
-				    (V2DI "TARGET_SSE4_2")])
-
 ;; Modes handled by vec_extract_even/odd pattern.
 (define_mode_iterator SSEMODE_EO
   [(V4SF "TARGET_SSE")
@@ -4552,71 +4553,57 @@ 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (define_expand "neg<mode>2"
-  [(set (match_operand:SSEMODEI 0 "register_operand" "")
-	(minus:SSEMODEI
+  [(set (match_operand:VI_128 0 "register_operand" "")
+	(minus:VI_128
 	  (match_dup 2)
-	  (match_operand:SSEMODEI 1 "nonimmediate_operand" "")))]
+	  (match_operand:VI_128 1 "nonimmediate_operand" "")))]
   "TARGET_SSE2"
   "operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));")
 
 (define_expand "<plusminus_insn><mode>3"
-  [(set (match_operand:SSEMODEI 0 "register_operand" "")
-	(plusminus:SSEMODEI
-	  (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
-	  (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
+  [(set (match_operand:VI_128 0 "register_operand" "")
+	(plusminus:VI_128
+	  (match_operand:VI_128 1 "nonimmediate_operand" "")
+	  (match_operand:VI_128 2 "nonimmediate_operand" "")))]
   "TARGET_SSE2"
   "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
 
-(define_insn "*avx_<plusminus_insn><mode>3"
-  [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
-	(plusminus:SSEMODEI
-	  (match_operand:SSEMODEI 1 "nonimmediate_operand" "<comm>x")
-	  (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
-  "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
-  "vp<plusminus_mnemonic><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "sseiadd")
-   (set_attr "prefix" "vex")
-   (set_attr "mode" "TI")])
-
 (define_insn "*<plusminus_insn><mode>3"
-  [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
-	(plusminus:SSEMODEI
-	  (match_operand:SSEMODEI 1 "nonimmediate_operand" "<comm>0")
-	  (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
+  [(set (match_operand:VI_128 0 "register_operand" "=x,x")
+	(plusminus:VI_128
+	  (match_operand:VI_128 1 "nonimmediate_operand" "<comm>0,x")
+	  (match_operand:VI_128 2 "nonimmediate_operand" "xm,xm")))]
   "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
-  "p<plusminus_mnemonic><ssevecsize>\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sseiadd")
-   (set_attr "prefix_data16" "1")
+  "@
+   p<plusminus_mnemonic><ssevecsize>\t{%2, %0|%0, %2}
+   vp<plusminus_mnemonic><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseiadd")
+   (set_attr "prefix_data16" "1,*")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
 (define_expand "sse2_<plusminus_insn><mode>3"
-  [(set (match_operand:SSEMODE12 0 "register_operand" "")
-	(sat_plusminus:SSEMODE12
-	  (match_operand:SSEMODE12 1 "nonimmediate_operand" "")
-	  (match_operand:SSEMODE12 2 "nonimmediate_operand" "")))]
+  [(set (match_operand:VI12_128 0 "register_operand" "")
+	(sat_plusminus:VI12_128
+	  (match_operand:VI12_128 1 "nonimmediate_operand" "")
+	  (match_operand:VI12_128 2 "nonimmediate_operand" "")))]
   "TARGET_SSE2"
   "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
 
-(define_insn "*avx_<plusminus_insn><mode>3"
-  [(set (match_operand:SSEMODE12 0 "register_operand" "=x")
-	(sat_plusminus:SSEMODE12
-	  (match_operand:SSEMODE12 1 "nonimmediate_operand" "<comm>x")
-	  (match_operand:SSEMODE12 2 "nonimmediate_operand" "xm")))]
-  "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
-  "vp<plusminus_mnemonic><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "sseiadd")
-   (set_attr "prefix" "vex")
-   (set_attr "mode" "TI")])
-
 (define_insn "*sse2_<plusminus_insn><mode>3"
-  [(set (match_operand:SSEMODE12 0 "register_operand" "=x")
-	(sat_plusminus:SSEMODE12
-	  (match_operand:SSEMODE12 1 "nonimmediate_operand" "<comm>0")
-	  (match_operand:SSEMODE12 2 "nonimmediate_operand" "xm")))]
+  [(set (match_operand:VI12_128 0 "register_operand" "=x,x")
+	(sat_plusminus:VI12_128
+	  (match_operand:VI12_128 1 "nonimmediate_operand" "<comm>0,x")
+	  (match_operand:VI12_128 2 "nonimmediate_operand" "xm,xm")))]
   "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
-  "p<plusminus_mnemonic><ssevecsize>\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sseiadd")
-   (set_attr "prefix_data16" "1")
+  "@
+   p<plusminus_mnemonic><ssevecsize>\t{%2, %0|%0, %2}
+   vp<plusminus_mnemonic><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseiadd")
+   (set_attr "prefix_data16" "1,*")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
 (define_insn_and_split "mulv16qi3"
@@ -4666,24 +4653,18 @@ 
   "TARGET_SSE2"
   "ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
 
-(define_insn "*avx_mulv8hi3"
-  [(set (match_operand:V8HI 0 "register_operand" "=x")
-	(mult:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "%x")
-		   (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
-  "TARGET_AVX && ix86_binary_operator_ok (MULT, V8HImode, operands)"
-  "vpmullw\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "sseimul")
-   (set_attr "prefix" "vex")
-   (set_attr "mode" "TI")])
-
 (define_insn "*mulv8hi3"
-  [(set (match_operand:V8HI 0 "register_operand" "=x")
-	(mult:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "%0")
-		   (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
+  [(set (match_operand:V8HI 0 "register_operand" "=x,x")
+	(mult:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "%0,x")
+		   (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")))]
   "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
-  "pmullw\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sseimul")
-   (set_attr "prefix_data16" "1")
+  "@
+   pmullw\t{%2, %0|%0, %2}
+   vpmullw\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseimul")
+   (set_attr "prefix_data16" "1,*")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
 (define_expand "<s>mulv8hi3_highpart"
@@ -4699,36 +4680,24 @@ 
   "TARGET_SSE2"
   "ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
 
-(define_insn "*avx_<s>mulv8hi3_highpart"
-  [(set (match_operand:V8HI 0 "register_operand" "=x")
-	(truncate:V8HI
-	  (lshiftrt:V8SI
-	    (mult:V8SI
-	      (any_extend:V8SI
-		(match_operand:V8HI 1 "nonimmediate_operand" "%x"))
-	      (any_extend:V8SI
-		(match_operand:V8HI 2 "nonimmediate_operand" "xm")))
-	    (const_int 16))))]
-  "TARGET_AVX && ix86_binary_operator_ok (MULT, V8HImode, operands)"
-  "vpmulh<u>w\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "sseimul")
-   (set_attr "prefix" "vex")
-   (set_attr "mode" "TI")])
-
 (define_insn "*<s>mulv8hi3_highpart"
-  [(set (match_operand:V8HI 0 "register_operand" "=x")
+  [(set (match_operand:V8HI 0 "register_operand" "=x,x")
 	(truncate:V8HI
 	  (lshiftrt:V8SI
 	    (mult:V8SI
 	      (any_extend:V8SI
-		(match_operand:V8HI 1 "nonimmediate_operand" "%0"))
+		(match_operand:V8HI 1 "nonimmediate_operand" "%0,x"))
 	      (any_extend:V8SI
-		(match_operand:V8HI 2 "nonimmediate_operand" "xm")))
+		(match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")))
 	    (const_int 16))))]
   "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
-  "pmulh<u>w\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sseimul")
-   (set_attr "prefix_data16" "1")
+  "@
+   pmulh<u>w\t{%2, %0|%0, %2}
+   vpmulh<u>w\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseimul")
+   (set_attr "prefix_data16" "1,*")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
 (define_expand "sse2_umulv2siv2di3"
@@ -4745,38 +4714,25 @@ 
   "TARGET_SSE2"
   "ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);")
 
-(define_insn "*avx_umulv2siv2di3"
-  [(set (match_operand:V2DI 0 "register_operand" "=x")
-	(mult:V2DI
-	  (zero_extend:V2DI
-	    (vec_select:V2SI
-	      (match_operand:V4SI 1 "nonimmediate_operand" "%x")
-	      (parallel [(const_int 0) (const_int 2)])))
-	  (zero_extend:V2DI
-	    (vec_select:V2SI
-	      (match_operand:V4SI 2 "nonimmediate_operand" "xm")
-	      (parallel [(const_int 0) (const_int 2)])))))]
-  "TARGET_AVX && ix86_binary_operator_ok (MULT, V4SImode, operands)"
-  "vpmuludq\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "sseimul")
-   (set_attr "prefix" "vex")
-   (set_attr "mode" "TI")])
-
 (define_insn "*sse2_umulv2siv2di3"
-  [(set (match_operand:V2DI 0 "register_operand" "=x")
+  [(set (match_operand:V2DI 0 "register_operand" "=x,x")
 	(mult:V2DI
 	  (zero_extend:V2DI
 	    (vec_select:V2SI
-	      (match_operand:V4SI 1 "nonimmediate_operand" "%0")
+	      (match_operand:V4SI 1 "nonimmediate_operand" "%0,x")
 	      (parallel [(const_int 0) (const_int 2)])))
 	  (zero_extend:V2DI
 	    (vec_select:V2SI
-	      (match_operand:V4SI 2 "nonimmediate_operand" "xm")
+	      (match_operand:V4SI 2 "nonimmediate_operand" "xm,xm")
 	      (parallel [(const_int 0) (const_int 2)])))))]
   "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V4SImode, operands)"
-  "pmuludq\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sseimul")
-   (set_attr "prefix_data16" "1")
+  "@
+   pmuludq\t{%2, %0|%0, %2}
+   vpmuludq\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseimul")
+   (set_attr "prefix_data16" "1,*")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
 (define_expand "sse4_1_mulv2siv2di3"
@@ -4793,39 +4749,26 @@ 
   "TARGET_SSE4_1"
   "ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);")
 
-(define_insn "*avx_mulv2siv2di3"
-  [(set (match_operand:V2DI 0 "register_operand" "=x")
-	(mult:V2DI
-	  (sign_extend:V2DI
-	    (vec_select:V2SI
-	      (match_operand:V4SI 1 "nonimmediate_operand" "%x")
-	      (parallel [(const_int 0) (const_int 2)])))
-	  (sign_extend:V2DI
-	    (vec_select:V2SI
-	      (match_operand:V4SI 2 "nonimmediate_operand" "xm")
-	      (parallel [(const_int 0) (const_int 2)])))))]
-  "TARGET_AVX && ix86_binary_operator_ok (MULT, V4SImode, operands)"
-  "vpmuldq\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "sseimul")
-   (set_attr "prefix_extra" "1")
-   (set_attr "prefix" "vex")
-   (set_attr "mode" "TI")])
-
 (define_insn "*sse4_1_mulv2siv2di3"
-  [(set (match_operand:V2DI 0 "register_operand" "=x")
+  [(set (match_operand:V2DI 0 "register_operand" "=x,x")
 	(mult:V2DI
 	  (sign_extend:V2DI
 	    (vec_select:V2SI
-	      (match_operand:V4SI 1 "nonimmediate_operand" "%0")
+	      (match_operand:V4SI 1 "nonimmediate_operand" "%0,x")
 	      (parallel [(const_int 0) (const_int 2)])))
 	  (sign_extend:V2DI
 	    (vec_select:V2SI
-	      (match_operand:V4SI 2 "nonimmediate_operand" "xm")
+	      (match_operand:V4SI 2 "nonimmediate_operand" "xm,xm")
 	      (parallel [(const_int 0) (const_int 2)])))))]
   "TARGET_SSE4_1 && ix86_binary_operator_ok (MULT, V4SImode, operands)"
-  "pmuldq\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sseimul")
+  "@
+   pmuldq\t{%2, %0|%0, %2}
+   vpmuldq\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseimul")
+   (set_attr "prefix_data16" "1,*")
    (set_attr "prefix_extra" "1")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
 (define_expand "sse2_pmaddwd"
@@ -4862,57 +4805,20 @@ 
   "TARGET_SSE2"
   "ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
 
-(define_insn "*avx_pmaddwd"
-  [(set (match_operand:V4SI 0 "register_operand" "=x")
-	(plus:V4SI
-	  (mult:V4SI
-	    (sign_extend:V4SI
-	      (vec_select:V4HI
-		(match_operand:V8HI 1 "nonimmediate_operand" "%x")
-		(parallel [(const_int 0)
-			   (const_int 2)
-			   (const_int 4)
-			   (const_int 6)])))
-	    (sign_extend:V4SI
-	      (vec_select:V4HI
-		(match_operand:V8HI 2 "nonimmediate_operand" "xm")
-		(parallel [(const_int 0)
-			   (const_int 2)
-			   (const_int 4)
-			   (const_int 6)]))))
-	  (mult:V4SI
-	    (sign_extend:V4SI
-	      (vec_select:V4HI (match_dup 1)
-		(parallel [(const_int 1)
-			   (const_int 3)
-			   (const_int 5)
-			   (const_int 7)])))
-	    (sign_extend:V4SI
-	      (vec_select:V4HI (match_dup 2)
-		(parallel [(const_int 1)
-			   (const_int 3)
-			   (const_int 5)
-			   (const_int 7)]))))))]
-  "TARGET_AVX && ix86_binary_operator_ok (MULT, V8HImode, operands)"
-  "vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "sseiadd")
-   (set_attr "prefix" "vex")
-   (set_attr "mode" "TI")])
-
 (define_insn "*sse2_pmaddwd"
-  [(set (match_operand:V4SI 0 "register_operand" "=x")
+  [(set (match_operand:V4SI 0 "register_operand" "=x,x")
 	(plus:V4SI
 	  (mult:V4SI
 	    (sign_extend:V4SI
 	      (vec_select:V4HI
-		(match_operand:V8HI 1 "nonimmediate_operand" "%0")
+		(match_operand:V8HI 1 "nonimmediate_operand" "%0,x")
 		(parallel [(const_int 0)
 			   (const_int 2)
 			   (const_int 4)
 			   (const_int 6)])))
 	    (sign_extend:V4SI
 	      (vec_select:V4HI
-		(match_operand:V8HI 2 "nonimmediate_operand" "xm")
+		(match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")
 		(parallel [(const_int 0)
 			   (const_int 2)
 			   (const_int 4)
@@ -4931,10 +4837,14 @@ 
 			   (const_int 5)
 			   (const_int 7)]))))))]
   "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
-  "pmaddwd\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sseiadd")
+  "@
+   pmaddwd\t{%2, %0|%0, %2}
+   vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseiadd")
    (set_attr "atom_unit" "simul")
-   (set_attr "prefix_data16" "1")
+   (set_attr "prefix_data16" "1,*")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
 (define_expand "mulv4si3"
@@ -4943,36 +4853,29 @@ 
 		   (match_operand:V4SI 2 "register_operand" "")))]
   "TARGET_SSE2"
 {
-  if (TARGET_SSE4_1 || TARGET_AVX)
+  if (TARGET_SSE4_1)
     ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);
 })
 
-(define_insn "*avx_mulv4si3"
-  [(set (match_operand:V4SI 0 "register_operand" "=x")
-	(mult:V4SI (match_operand:V4SI 1 "nonimmediate_operand" "%x")
-		   (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
-  "TARGET_AVX && ix86_binary_operator_ok (MULT, V4SImode, operands)"
-  "vpmulld\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "sseimul")
-   (set_attr "prefix_extra" "1")
-   (set_attr "prefix" "vex")
-   (set_attr "mode" "TI")])
-
 (define_insn "*sse4_1_mulv4si3"
-  [(set (match_operand:V4SI 0 "register_operand" "=x")
-	(mult:V4SI (match_operand:V4SI 1 "nonimmediate_operand" "%0")
-		   (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
+  [(set (match_operand:V4SI 0 "register_operand" "=x,x")
+	(mult:V4SI (match_operand:V4SI 1 "nonimmediate_operand" "%0,x")
+		   (match_operand:V4SI 2 "nonimmediate_operand" "xm,xm")))]
   "TARGET_SSE4_1 && ix86_binary_operator_ok (MULT, V4SImode, operands)"
-  "pmulld\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sseimul")
+  "@
+   pmulld\t{%2, %0|%0, %2}
+   vpmulld\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseimul")
    (set_attr "prefix_extra" "1")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
 (define_insn_and_split "*sse2_mulv4si3"
   [(set (match_operand:V4SI 0 "register_operand" "")
 	(mult:V4SI (match_operand:V4SI 1 "register_operand" "")
 		   (match_operand:V4SI 2 "register_operand" "")))]
-  "TARGET_SSE2 && !TARGET_SSE4_1 && !TARGET_AVX
+  "TARGET_SSE2
    && can_create_pseudo_p ()"
   "#"
   "&& 1"
@@ -5313,159 +5216,67 @@ 
   DONE;
 })
 
-(define_insn "*avx_ashr<mode>3"
-  [(set (match_operand:SSEMODE24 0 "register_operand" "=x")
-	(ashiftrt:SSEMODE24
-	  (match_operand:SSEMODE24 1 "register_operand" "x")
-	  (match_operand:SI 2 "nonmemory_operand" "xN")))]
-  "TARGET_AVX"
-  "vpsra<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "sseishft")
-   (set_attr "prefix" "vex")
-   (set (attr "length_immediate")
-     (if_then_else (match_operand 2 "const_int_operand" "")
-       (const_string "1")
-       (const_string "0")))
-   (set_attr "mode" "TI")])
-
 (define_insn "ashr<mode>3"
-  [(set (match_operand:SSEMODE24 0 "register_operand" "=x")
-	(ashiftrt:SSEMODE24
-	  (match_operand:SSEMODE24 1 "register_operand" "0")
-	  (match_operand:SI 2 "nonmemory_operand" "xN")))]
+  [(set (match_operand:VI24_128 0 "register_operand" "=x,x")
+	(ashiftrt:VI24_128
+	  (match_operand:VI24_128 1 "register_operand" "0,x")
+	  (match_operand:SI 2 "nonmemory_operand" "xN,xN")))]
   "TARGET_SSE2"
-  "psra<ssevecsize>\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sseishft")
-   (set_attr "prefix_data16" "1")
+  "@
+   psra<ssevecsize>\t{%2, %0|%0, %2}
+   vpsra<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseishft")
    (set (attr "length_immediate")
      (if_then_else (match_operand 2 "const_int_operand" "")
        (const_string "1")
        (const_string "0")))
+   (set_attr "prefix_data16" "1,*")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
-(define_insn "*avx_lshrv1ti3"
-  [(set (match_operand:V1TI 0 "register_operand" "=x")
- 	(lshiftrt:V1TI
-	 (match_operand:V1TI 1 "register_operand" "x")
-	 (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
-  "TARGET_AVX"
-{
-  operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
-  return "vpsrldq\t{%2, %1, %0|%0, %1, %2}";
-}
-  [(set_attr "type" "sseishft")
-   (set_attr "prefix" "vex")
-   (set_attr "length_immediate" "1")
-   (set_attr "mode" "TI")])
-
-(define_insn "*avx_lshr<mode>3"
-  [(set (match_operand:SSEMODE248 0 "register_operand" "=x")
-	(lshiftrt:SSEMODE248
-	  (match_operand:SSEMODE248 1 "register_operand" "x")
-	  (match_operand:SI 2 "nonmemory_operand" "xN")))]
-  "TARGET_AVX"
-  "vpsrl<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "sseishft")
-   (set_attr "prefix" "vex")
-   (set (attr "length_immediate")
-     (if_then_else (match_operand 2 "const_int_operand" "")
-       (const_string "1")
-       (const_string "0")))
-   (set_attr "mode" "TI")])
-
-(define_insn "sse2_lshrv1ti3"
-  [(set (match_operand:V1TI 0 "register_operand" "=x")
- 	(lshiftrt:V1TI
-	 (match_operand:V1TI 1 "register_operand" "0")
-	 (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
-  "TARGET_SSE2"
-{
-  operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
-  return "psrldq\t{%2, %0|%0, %2}";
-}
-  [(set_attr "type" "sseishft")
-   (set_attr "prefix_data16" "1")
-   (set_attr "length_immediate" "1")
-   (set_attr "atom_unit" "sishuf")
-   (set_attr "mode" "TI")])
-
 (define_insn "lshr<mode>3"
-  [(set (match_operand:SSEMODE248 0 "register_operand" "=x")
-	(lshiftrt:SSEMODE248
-	  (match_operand:SSEMODE248 1 "register_operand" "0")
-	  (match_operand:SI 2 "nonmemory_operand" "xN")))]
+  [(set (match_operand:VI248_128 0 "register_operand" "=x,x")
+	(lshiftrt:VI248_128
+	  (match_operand:VI248_128 1 "register_operand" "0,x")
+	  (match_operand:SI 2 "nonmemory_operand" "xN,xN")))]
   "TARGET_SSE2"
-  "psrl<ssevecsize>\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sseishft")
-   (set_attr "prefix_data16" "1")
+  "@
+   psrl<ssevecsize>\t{%2, %0|%0, %2}
+   vpsrl<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseishft")
    (set (attr "length_immediate")
      (if_then_else (match_operand 2 "const_int_operand" "")
        (const_string "1")
        (const_string "0")))
+   (set_attr "prefix_data16" "1,*")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
-(define_insn "*avx_ashlv1ti3"
-  [(set (match_operand:V1TI 0 "register_operand" "=x")
-	(ashift:V1TI (match_operand:V1TI 1 "register_operand" "x")
-		     (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
-  "TARGET_AVX"
-{
-  operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
-  return "vpslldq\t{%2, %1, %0|%0, %1, %2}";
-}
-  [(set_attr "type" "sseishft")
-   (set_attr "prefix" "vex")
-   (set_attr "length_immediate" "1")
-   (set_attr "mode" "TI")])
-
-(define_insn "*avx_ashl<mode>3"
-  [(set (match_operand:SSEMODE248 0 "register_operand" "=x")
-	(ashift:SSEMODE248
-	  (match_operand:SSEMODE248 1 "register_operand" "x")
-	  (match_operand:SI 2 "nonmemory_operand" "xN")))]
-  "TARGET_AVX"
-  "vpsll<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "sseishft")
-   (set_attr "prefix" "vex")
-   (set (attr "length_immediate")
-     (if_then_else (match_operand 2 "const_int_operand" "")
-       (const_string "1")
-       (const_string "0")))
-   (set_attr "mode" "TI")])
-
-(define_insn "sse2_ashlv1ti3"
-  [(set (match_operand:V1TI 0 "register_operand" "=x")
-	(ashift:V1TI (match_operand:V1TI 1 "register_operand" "0")
-		     (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
-  "TARGET_SSE2"
-{
-  operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
-  return "pslldq\t{%2, %0|%0, %2}";
-}
-  [(set_attr "type" "sseishft")
-   (set_attr "prefix_data16" "1")
-   (set_attr "length_immediate" "1")
-   (set_attr "mode" "TI")])
-
 (define_insn "ashl<mode>3"
-  [(set (match_operand:SSEMODE248 0 "register_operand" "=x")
-	(ashift:SSEMODE248
-	  (match_operand:SSEMODE248 1 "register_operand" "0")
-	  (match_operand:SI 2 "nonmemory_operand" "xN")))]
+  [(set (match_operand:VI248_128 0 "register_operand" "=x,x")
+	(ashift:VI248_128
+	  (match_operand:VI248_128 1 "register_operand" "0,x")
+	  (match_operand:SI 2 "nonmemory_operand" "xN,xN")))]
   "TARGET_SSE2"
-  "psll<ssevecsize>\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sseishft")
-   (set_attr "prefix_data16" "1")
+  "@
+   psll<ssevecsize>\t{%2, %0|%0, %2}
+   vpsll<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseishft")
    (set (attr "length_immediate")
      (if_then_else (match_operand 2 "const_int_operand" "")
        (const_string "1")
        (const_string "0")))
+   (set_attr "prefix_data16" "1,*")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
 (define_expand "vec_shl_<mode>"
-  [(set (match_operand:SSEMODEI 0 "register_operand" "")
+  [(set (match_operand:VI_128 0 "register_operand" "")
         (ashift:V1TI
-	 (match_operand:SSEMODEI 1 "register_operand" "")
+	 (match_operand:VI_128 1 "register_operand" "")
 	 (match_operand:SI 2 "const_0_to_255_mul_8_operand" "")))]
   "TARGET_SSE2"
 {
@@ -5473,10 +5284,36 @@ 
   operands[1] = gen_lowpart (V1TImode, operands[1]);
 })
 
+(define_insn "sse2_ashlv1ti3"
+  [(set (match_operand:V1TI 0 "register_operand" "=x,x")
+	(ashift:V1TI
+	 (match_operand:V1TI 1 "register_operand" "0,x")
+	 (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n,n")))]
+  "TARGET_SSE2"
+{
+  operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
+
+  switch (which_alternative)
+    {
+    case 0:
+      return "pslldq\t{%2, %0|%0, %2}";
+    case 1:
+      return "vpslldq\t{%2, %1, %0|%0, %1, %2}";
+    default:
+      gcc_unreachable ();
+    }
+}
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseishft")
+   (set_attr "length_immediate" "1")
+   (set_attr "prefix_data16" "1,*")
+   (set_attr "prefix" "orig,vex")
+   (set_attr "mode" "TI")])
+
 (define_expand "vec_shr_<mode>"
-  [(set (match_operand:SSEMODEI 0 "register_operand" "")
+  [(set (match_operand:VI_128 0 "register_operand" "")
         (lshiftrt:V1TI
-	 (match_operand:SSEMODEI 1 "register_operand" "")
+	 (match_operand:VI_128 1 "register_operand" "")
 	 (match_operand:SI 2 "const_0_to_255_mul_8_operand" "")))]
   "TARGET_SSE2"
 {
@@ -5484,109 +5321,105 @@ 
   operands[1] = gen_lowpart (V1TImode, operands[1]);
 })
 
-(define_insn "*avx_<code><mode>3"
-  [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
-	(umaxmin:SSEMODE124
-	  (match_operand:SSEMODE124 1 "nonimmediate_operand" "%x")
-	  (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))]
-  "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
-  "vp<maxmin_int><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "sseiadd")
-   (set (attr "prefix_extra")
-     (if_then_else (match_operand:V16QI 0 "" "")
-       (const_string "0")
-       (const_string "1")))
-   (set_attr "prefix" "vex")
-   (set_attr "mode" "TI")])
-
-(define_expand "<code>v16qi3"
-  [(set (match_operand:V16QI 0 "register_operand" "")
-	(umaxmin:V16QI
-	  (match_operand:V16QI 1 "nonimmediate_operand" "")
-	  (match_operand:V16QI 2 "nonimmediate_operand" "")))]
+(define_insn "sse2_lshrv1ti3"
+  [(set (match_operand:V1TI 0 "register_operand" "=x,x")
+ 	(lshiftrt:V1TI
+	 (match_operand:V1TI 1 "register_operand" "0,x")
+	 (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n,n")))]
   "TARGET_SSE2"
-  "ix86_fixup_binary_operands_no_copy (<CODE>, V16QImode, operands);")
+{
+  operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
 
-(define_insn "*<code>v16qi3"
-  [(set (match_operand:V16QI 0 "register_operand" "=x")
-	(umaxmin:V16QI
-	  (match_operand:V16QI 1 "nonimmediate_operand" "%0")
-	  (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
-  "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V16QImode, operands)"
-  "p<maxmin_int>b\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sseiadd")
-   (set_attr "prefix_data16" "1")
+  switch (which_alternative)
+    {
+    case 0:
+      return "psrldq\t{%2, %0|%0, %2}";
+    case 1:
+      return "vpsrldq\t{%2, %1, %0|%0, %1, %2}";
+    default:
+      gcc_unreachable ();
+    }
+}
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseishft")
+   (set_attr "length_immediate" "1")
+   (set_attr "atom_unit" "sishuf")
+   (set_attr "prefix_data16" "1,*")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
-(define_insn "*avx_<code><mode>3"
-  [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
-	(smaxmin:SSEMODE124
-	  (match_operand:SSEMODE124 1 "nonimmediate_operand" "%x")
-	  (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))]
-  "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
-  "vp<maxmin_int><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "sseiadd")
-   (set (attr "prefix_extra")
-     (if_then_else (match_operand:V8HI 0 "" "")
-       (const_string "0")
-       (const_string "1")))
-   (set_attr "prefix" "vex")
+(define_insn "*sse4_1_<code><mode>3"
+  [(set (match_operand:VI14_128 0 "register_operand" "=x,x")
+	(smaxmin:VI14_128
+	  (match_operand:VI14_128 1 "nonimmediate_operand" "%0,x")
+	  (match_operand:VI14_128 2 "nonimmediate_operand" "xm,xm")))]
+  "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+  "@
+   p<maxmin_int><ssevecsize>\t{%2, %0|%0, %2}
+   vp<maxmin_int><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseiadd")
+   (set_attr "prefix_extra" "1,*")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
-(define_expand "<code>v8hi3"
-  [(set (match_operand:V8HI 0 "register_operand" "")
-	(smaxmin:V8HI
-	  (match_operand:V8HI 1 "nonimmediate_operand" "")
-	  (match_operand:V8HI 2 "nonimmediate_operand" "")))]
-  "TARGET_SSE2"
-  "ix86_fixup_binary_operands_no_copy (<CODE>, V8HImode, operands);")
-
 (define_insn "*<code>v8hi3"
-  [(set (match_operand:V8HI 0 "register_operand" "=x")
+  [(set (match_operand:V8HI 0 "register_operand" "=x,x")
 	(smaxmin:V8HI
-	  (match_operand:V8HI 1 "nonimmediate_operand" "%0")
-	  (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
+	  (match_operand:V8HI 1 "nonimmediate_operand" "%0,x")
+	  (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")))]
   "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V8HImode, operands)"
-  "p<maxmin_int>w\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sseiadd")
-   (set_attr "prefix_data16" "1")
+  "@
+   p<maxmin_int>w\t{%2, %0|%0, %2}
+   vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseiadd")
+   (set_attr "prefix_data16" "1,*")
+   (set_attr "prefix_extra" "*,1")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
-(define_expand "umaxv8hi3"
-  [(set (match_operand:V8HI 0 "register_operand" "")
-	(umax:V8HI (match_operand:V8HI 1 "register_operand" "")
-		   (match_operand:V8HI 2 "nonimmediate_operand" "")))]
+(define_expand "smax<mode>3"
+  [(set (match_operand:VI14_128 0 "register_operand" "")
+	(smax:VI14_128 (match_operand:VI14_128 1 "register_operand" "")
+		       (match_operand:VI14_128 2 "register_operand" "")))]
   "TARGET_SSE2"
 {
   if (TARGET_SSE4_1)
-    ix86_fixup_binary_operands_no_copy (UMAX, V8HImode, operands);
+    ix86_fixup_binary_operands_no_copy (SMAX, <MODE>mode, operands);
   else
     {
-      rtx op0 = operands[0], op2 = operands[2], op3 = op0;
-      if (rtx_equal_p (op3, op2))
-	op3 = gen_reg_rtx (V8HImode);
-      emit_insn (gen_sse2_ussubv8hi3 (op3, operands[1], op2));
-      emit_insn (gen_addv8hi3 (op0, op3, op2));
+      rtx xops[6];
+      bool ok;
+
+      xops[0] = operands[0];
+      xops[1] = operands[1];
+      xops[2] = operands[2];
+      xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
+      xops[4] = operands[1];
+      xops[5] = operands[2];
+      ok = ix86_expand_int_vcond (xops);
+      gcc_assert (ok);
       DONE;
     }
 })
 
-(define_expand "smax<mode>3"
-  [(set (match_operand:SSEMODE14 0 "register_operand" "")
-	(smax:SSEMODE14 (match_operand:SSEMODE14 1 "register_operand" "")
-			(match_operand:SSEMODE14 2 "register_operand" "")))]
+(define_expand "smin<mode>3"
+  [(set (match_operand:VI14_128 0 "register_operand" "")
+	(smin:VI14_128 (match_operand:VI14_128 1 "register_operand" "")
+		       (match_operand:VI14_128 2 "register_operand" "")))]
   "TARGET_SSE2"
 {
   if (TARGET_SSE4_1)
-    ix86_fixup_binary_operands_no_copy (SMAX, <MODE>mode, operands);
+    ix86_fixup_binary_operands_no_copy (SMIN, <MODE>mode, operands);
   else
     {
       rtx xops[6];
       bool ok;
 
       xops[0] = operands[0];
-      xops[1] = operands[1];
-      xops[2] = operands[2];
+      xops[1] = operands[2];
+      xops[2] = operands[1];
       xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
       xops[4] = operands[1];
       xops[5] = operands[2];
@@ -5596,16 +5429,13 @@ 
     }
 })
 
-(define_insn "*sse4_1_<code><mode>3"
-  [(set (match_operand:SSEMODE14 0 "register_operand" "=x")
-	(smaxmin:SSEMODE14
-	  (match_operand:SSEMODE14 1 "nonimmediate_operand" "%0")
-	  (match_operand:SSEMODE14 2 "nonimmediate_operand" "xm")))]
-  "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
-  "p<maxmin_int><ssevecsize>\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sseiadd")
-   (set_attr "prefix_extra" "1")
-   (set_attr "mode" "TI")])
+(define_expand "<code>v8hi3"
+  [(set (match_operand:V8HI 0 "register_operand" "")
+	(smaxmin:V8HI
+	  (match_operand:V8HI 1 "nonimmediate_operand" "")
+	  (match_operand:V8HI 2 "nonimmediate_operand" "")))]
+  "TARGET_SSE2"
+  "ix86_fixup_binary_operands_no_copy (<CODE>, V8HImode, operands);")
 
 (define_expand "smaxv2di3"
   [(set (match_operand:V2DI 0 "register_operand" "")
@@ -5627,6 +5457,84 @@ 
   DONE;
 })
 
+(define_expand "sminv2di3"
+  [(set (match_operand:V2DI 0 "register_operand" "")
+	(smin:V2DI (match_operand:V2DI 1 "register_operand" "")
+		   (match_operand:V2DI 2 "register_operand" "")))]
+  "TARGET_SSE4_2"
+{
+  rtx xops[6];
+  bool ok;
+
+  xops[0] = operands[0];
+  xops[1] = operands[2];
+  xops[2] = operands[1];
+  xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
+  xops[4] = operands[1];
+  xops[5] = operands[2];
+  ok = ix86_expand_int_vcond (xops);
+  gcc_assert (ok);
+  DONE;
+})
+
+(define_insn "*sse4_1_<code><mode>3"
+  [(set (match_operand:VI24_128 0 "register_operand" "=x,x")
+	(umaxmin:VI24_128
+	  (match_operand:VI24_128 1 "nonimmediate_operand" "%0,x")
+	  (match_operand:VI24_128 2 "nonimmediate_operand" "xm,xm")))]
+  "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+  "@
+   p<maxmin_int><ssevecsize>\t{%2, %0|%0, %2}
+   vp<maxmin_int><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseiadd")
+   (set_attr "prefix_extra" "1,*")
+   (set_attr "prefix" "orig,vex")
+   (set_attr "mode" "TI")])
+
+(define_insn "*<code>v16qi3"
+  [(set (match_operand:V16QI 0 "register_operand" "=x,x")
+	(umaxmin:V16QI
+	  (match_operand:V16QI 1 "nonimmediate_operand" "%0,x")
+	  (match_operand:V16QI 2 "nonimmediate_operand" "xm,xm")))]
+  "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V16QImode, operands)"
+  "@
+   p<maxmin_int>b\t{%2, %0|%0, %2}
+   vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseiadd")
+   (set_attr "prefix_data16" "1,*")
+   (set_attr "prefix_extra" "*,1")
+   (set_attr "prefix" "orig,vex")
+   (set_attr "mode" "TI")])
+
+(define_expand "<code>v16qi3"
+  [(set (match_operand:V16QI 0 "register_operand" "")
+	(umaxmin:V16QI
+	  (match_operand:V16QI 1 "nonimmediate_operand" "")
+	  (match_operand:V16QI 2 "nonimmediate_operand" "")))]
+  "TARGET_SSE2"
+  "ix86_fixup_binary_operands_no_copy (<CODE>, V16QImode, operands);")
+
+(define_expand "umaxv8hi3"
+  [(set (match_operand:V8HI 0 "register_operand" "")
+	(umax:V8HI (match_operand:V8HI 1 "register_operand" "")
+		   (match_operand:V8HI 2 "nonimmediate_operand" "")))]
+  "TARGET_SSE2"
+{
+  if (TARGET_SSE4_1)
+    ix86_fixup_binary_operands_no_copy (UMAX, V8HImode, operands);
+  else
+    {
+      rtx op0 = operands[0], op2 = operands[2], op3 = op0;
+      if (rtx_equal_p (op3, op2))
+	op3 = gen_reg_rtx (V8HImode);
+      emit_insn (gen_sse2_ussubv8hi3 (op3, operands[1], op2));
+      emit_insn (gen_addv8hi3 (op0, op3, op2));
+      DONE;
+    }
+})
+
 (define_expand "umaxv4si3"
   [(set (match_operand:V4SI 0 "register_operand" "")
 	(umax:V4SI (match_operand:V4SI 1 "register_operand" "")
@@ -5652,45 +5560,14 @@ 
     }
 })
 
-(define_insn "*sse4_1_<code><mode>3"
-  [(set (match_operand:SSEMODE24 0 "register_operand" "=x")
-	(umaxmin:SSEMODE24
-	  (match_operand:SSEMODE24 1 "nonimmediate_operand" "%0")
-	  (match_operand:SSEMODE24 2 "nonimmediate_operand" "xm")))]
-  "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
-  "p<maxmin_int><ssevecsize>\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sseiadd")
-   (set_attr "prefix_extra" "1")
-   (set_attr "mode" "TI")])
-
-(define_expand "umaxv2di3"
-  [(set (match_operand:V2DI 0 "register_operand" "")
-	(umax:V2DI (match_operand:V2DI 1 "register_operand" "")
-		   (match_operand:V2DI 2 "register_operand" "")))]
-  "TARGET_SSE4_2"
-{
-  rtx xops[6];
-  bool ok;
-
-  xops[0] = operands[0];
-  xops[1] = operands[1];
-  xops[2] = operands[2];
-  xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
-  xops[4] = operands[1];
-  xops[5] = operands[2];
-  ok = ix86_expand_int_vcond (xops);
-  gcc_assert (ok);
-  DONE;
-})
-
-(define_expand "smin<mode>3"
-  [(set (match_operand:SSEMODE14 0 "register_operand" "")
-	(smin:SSEMODE14 (match_operand:SSEMODE14 1 "register_operand" "")
-			(match_operand:SSEMODE14 2 "register_operand" "")))]
+(define_expand "umin<mode>3"
+  [(set (match_operand:VI24_128 0 "register_operand" "")
+	(umin:VI24_128 (match_operand:VI24_128 1 "register_operand" "")
+		       (match_operand:VI24_128 2 "register_operand" "")))]
   "TARGET_SSE2"
 {
   if (TARGET_SSE4_1)
-    ix86_fixup_binary_operands_no_copy (SMIN, <MODE>mode, operands);
+    ix86_fixup_binary_operands_no_copy (UMIN, <MODE>mode, operands);
   else
     {
       rtx xops[6];
@@ -5699,7 +5576,7 @@ 
       xops[0] = operands[0];
       xops[1] = operands[2];
       xops[2] = operands[1];
-      xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
+      xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
       xops[4] = operands[1];
       xops[5] = operands[2];
       ok = ix86_expand_int_vcond (xops);
@@ -5708,9 +5585,9 @@ 
     }
 })
 
-(define_expand "sminv2di3"
+(define_expand "umaxv2di3"
   [(set (match_operand:V2DI 0 "register_operand" "")
-	(smin:V2DI (match_operand:V2DI 1 "register_operand" "")
+	(umax:V2DI (match_operand:V2DI 1 "register_operand" "")
 		   (match_operand:V2DI 2 "register_operand" "")))]
   "TARGET_SSE4_2"
 {
@@ -5718,9 +5595,9 @@ 
   bool ok;
 
   xops[0] = operands[0];
-  xops[1] = operands[2];
-  xops[2] = operands[1];
-  xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
+  xops[1] = operands[1];
+  xops[2] = operands[2];
+  xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
   xops[4] = operands[1];
   xops[5] = operands[2];
   ok = ix86_expand_int_vcond (xops);
@@ -5728,31 +5605,6 @@ 
   DONE;
 })
 
-(define_expand "umin<mode>3"
-  [(set (match_operand:SSEMODE24 0 "register_operand" "")
-	(umin:SSEMODE24 (match_operand:SSEMODE24 1 "register_operand" "")
-			(match_operand:SSEMODE24 2 "register_operand" "")))]
-  "TARGET_SSE2"
-{
-  if (TARGET_SSE4_1)
-    ix86_fixup_binary_operands_no_copy (UMIN, <MODE>mode, operands);
-  else
-    {
-      rtx xops[6];
-      bool ok;
-
-      xops[0] = operands[0];
-      xops[1] = operands[2];
-      xops[2] = operands[1];
-      xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
-      xops[4] = operands[1];
-      xops[5] = operands[2];
-      ok = ix86_expand_int_vcond (xops);
-      gcc_assert (ok);
-      DONE;
-    }
-})
-
 (define_expand "uminv2di3"
   [(set (match_operand:V2DI 0 "register_operand" "")
 	(umin:V2DI (match_operand:V2DI 1 "register_operand" "")
@@ -5779,41 +5631,45 @@ 
 ;;
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-(define_expand "sse2_eq<mode>3"
-  [(set (match_operand:SSEMODE124 0 "register_operand" "")
-	(eq:SSEMODE124
-	  (match_operand:SSEMODE124 1 "nonimmediate_operand" "")
-	  (match_operand:SSEMODE124 2 "nonimmediate_operand" "")))]
-  "TARGET_SSE2 && !TARGET_XOP "
-  "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
-
-(define_insn "*avx_eq<mode>3"
-  [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
-	(eq:SSEMODE1248
-	  (match_operand:SSEMODE1248 1 "nonimmediate_operand" "%x")
-	  (match_operand:SSEMODE1248 2 "nonimmediate_operand" "xm")))]
-  "TARGET_AVX && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
-  "vpcmpeq<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "ssecmp")
-   (set (attr "prefix_extra")
-     (if_then_else (match_operand:V2DI 0 "" "")
-       (const_string "1")
-       (const_string "*")))
-   (set_attr "prefix" "vex")
+(define_insn "*sse4_1_eqv2di3"
+  [(set (match_operand:V2DI 0 "register_operand" "=x,x")
+	(eq:V2DI
+	  (match_operand:V2DI 1 "nonimmediate_operand" "%0,x")
+	  (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")))]
+  "TARGET_SSE4_1 && ix86_binary_operator_ok (EQ, V2DImode, operands)"
+  "@
+   pcmpeqq\t{%2, %0|%0, %2}
+   vpcmpeqq\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "ssecmp")
+   (set_attr "prefix_extra" "1")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
 (define_insn "*sse2_eq<mode>3"
-  [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
-	(eq:SSEMODE124
-	  (match_operand:SSEMODE124 1 "nonimmediate_operand" "%0")
-	  (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))]
+  [(set (match_operand:VI124_128 0 "register_operand" "=x,x")
+	(eq:VI124_128
+	  (match_operand:VI124_128 1 "nonimmediate_operand" "%0,x")
+	  (match_operand:VI124_128 2 "nonimmediate_operand" "xm,xm")))]
   "TARGET_SSE2 && !TARGET_XOP
    && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
-  "pcmpeq<ssevecsize>\t{%2, %0|%0, %2}"
-  [(set_attr "type" "ssecmp")
-   (set_attr "prefix_data16" "1")
+  "@
+   pcmpeq<ssevecsize>\t{%2, %0|%0, %2}
+   vpcmpeq<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "ssecmp")
+   (set_attr "prefix_data16" "1,*")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
+(define_expand "sse2_eq<mode>3"
+  [(set (match_operand:VI124_128 0 "register_operand" "")
+	(eq:VI124_128
+	  (match_operand:VI124_128 1 "nonimmediate_operand" "")
+	  (match_operand:VI124_128 2 "nonimmediate_operand" "")))]
+  "TARGET_SSE2 && !TARGET_XOP "
+  "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
+
 (define_expand "sse4_1_eqv2di3"
   [(set (match_operand:V2DI 0 "register_operand" "")
 	(eq:V2DI
@@ -5822,62 +5678,44 @@ 
   "TARGET_SSE4_1"
   "ix86_fixup_binary_operands_no_copy (EQ, V2DImode, operands);")
 
-(define_insn "*sse4_1_eqv2di3"
-  [(set (match_operand:V2DI 0 "register_operand" "=x")
-	(eq:V2DI
-	  (match_operand:V2DI 1 "nonimmediate_operand" "%0")
-	  (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
-  "TARGET_SSE4_1 && ix86_binary_operator_ok (EQ, V2DImode, operands)"
-  "pcmpeqq\t{%2, %0|%0, %2}"
-  [(set_attr "type" "ssecmp")
+(define_insn "sse4_2_gtv2di3"
+  [(set (match_operand:V2DI 0 "register_operand" "=x,x")
+	(gt:V2DI
+	  (match_operand:V2DI 1 "register_operand" "0,x")
+	  (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")))]
+  "TARGET_SSE4_2"
+  "@
+   pcmpgtq\t{%2, %0|%0, %2}
+   vpcmpgtq\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "ssecmp")
    (set_attr "prefix_extra" "1")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
-(define_insn "*avx_gt<mode>3"
-  [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
-	(gt:SSEMODE1248
-	  (match_operand:SSEMODE1248 1 "register_operand" "x")
-	  (match_operand:SSEMODE1248 2 "nonimmediate_operand" "xm")))]
-  "TARGET_AVX"
-  "vpcmpgt<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "ssecmp")
-   (set (attr "prefix_extra")
-     (if_then_else (match_operand:V2DI 0 "" "")
-       (const_string "1")
-       (const_string "*")))
-   (set_attr "prefix" "vex")
-   (set_attr "mode" "TI")])
-
 (define_insn "sse2_gt<mode>3"
-  [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
-	(gt:SSEMODE124
-	  (match_operand:SSEMODE124 1 "register_operand" "0")
-	  (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))]
+  [(set (match_operand:VI124_128 0 "register_operand" "=x,x")
+	(gt:VI124_128
+	  (match_operand:VI124_128 1 "register_operand" "0,x")
+	  (match_operand:VI124_128 2 "nonimmediate_operand" "xm,xm")))]
   "TARGET_SSE2 && !TARGET_XOP"
-  "pcmpgt<ssevecsize>\t{%2, %0|%0, %2}"
-  [(set_attr "type" "ssecmp")
-   (set_attr "prefix_data16" "1")
+  "@
+   pcmpgt<ssevecsize>\t{%2, %0|%0, %2}
+   vpcmpgt<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "ssecmp")
+   (set_attr "prefix_data16" "1,*")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
-(define_insn "sse4_2_gtv2di3"
-  [(set (match_operand:V2DI 0 "register_operand" "=x")
-	(gt:V2DI
-	  (match_operand:V2DI 1 "register_operand" "0")
-	  (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
-  "TARGET_SSE4_2"
-  "pcmpgtq\t{%2, %0|%0, %2}"
-  [(set_attr "type" "ssecmp")
-   (set_attr "prefix_extra" "1")
-   (set_attr "mode" "TI")])
-
 (define_expand "vcond<mode>"
-  [(set (match_operand:SSEMODE124C8 0 "register_operand" "")
-        (if_then_else:SSEMODE124C8
+  [(set (match_operand:VI124_128 0 "register_operand" "")
+        (if_then_else:VI124_128
           (match_operator 3 ""
-            [(match_operand:SSEMODE124C8 4 "nonimmediate_operand" "")
-             (match_operand:SSEMODE124C8 5 "nonimmediate_operand" "")])
-          (match_operand:SSEMODE124C8 1 "general_operand" "")
-          (match_operand:SSEMODE124C8 2 "general_operand" "")))]
+            [(match_operand:VI124_128 4 "nonimmediate_operand" "")
+             (match_operand:VI124_128 5 "nonimmediate_operand" "")])
+          (match_operand:VI124_128 1 "general_operand" "")
+          (match_operand:VI124_128 2 "general_operand" "")))]
   "TARGET_SSE2"
 {
   bool ok = ix86_expand_int_vcond (operands);
@@ -5885,14 +5723,29 @@ 
   DONE;
 })
 
+(define_expand "vcondv2di"
+  [(set (match_operand:V2DI 0 "register_operand" "")
+        (if_then_else:V2DI
+          (match_operator 3 ""
+            [(match_operand:V2DI 4 "nonimmediate_operand" "")
+             (match_operand:V2DI 5 "nonimmediate_operand" "")])
+          (match_operand:V2DI 1 "general_operand" "")
+          (match_operand:V2DI 2 "general_operand" "")))]
+  "TARGET_SSE4_2"
+{
+  bool ok = ix86_expand_int_vcond (operands);
+  gcc_assert (ok);
+  DONE;
+})
+
 (define_expand "vcondu<mode>"
-  [(set (match_operand:SSEMODE124C8 0 "register_operand" "")
-        (if_then_else:SSEMODE124C8
+  [(set (match_operand:VI124_128 0 "register_operand" "")
+        (if_then_else:VI124_128
           (match_operator 3 ""
-            [(match_operand:SSEMODE124C8 4 "nonimmediate_operand" "")
-             (match_operand:SSEMODE124C8 5 "nonimmediate_operand" "")])
-          (match_operand:SSEMODE124C8 1 "general_operand" "")
-          (match_operand:SSEMODE124C8 2 "general_operand" "")))]
+            [(match_operand:VI124_128 4 "nonimmediate_operand" "")
+             (match_operand:VI124_128 5 "nonimmediate_operand" "")])
+          (match_operand:VI124_128 1 "general_operand" "")
+          (match_operand:VI124_128 2 "general_operand" "")))]
   "TARGET_SSE2"
 {
   bool ok = ix86_expand_int_vcond (operands);
@@ -5900,6 +5753,21 @@ 
   DONE;
 })
 
+(define_expand "vconduv2di"
+  [(set (match_operand:V2DI 0 "register_operand" "")
+        (if_then_else:V2DI
+          (match_operator 3 ""
+            [(match_operand:V2DI 4 "nonimmediate_operand" "")
+             (match_operand:V2DI 5 "nonimmediate_operand" "")])
+          (match_operand:V2DI 1 "general_operand" "")
+          (match_operand:V2DI 2 "general_operand" "")))]
+  "TARGET_SSE4_2"
+{
+  bool ok = ix86_expand_int_vcond (operands);
+  gcc_assert (ok);
+  DONE;
+})
+
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
 ;; Parallel bitwise logical operations