Patchwork DMA misaligned error with device 4

login
register
mail settings
Submitter Sven Krauss
Date April 11, 2011, 3:18 p.m.
Message ID <1631427694.1700754.1302535107434.JavaMail.fmail@mwmweb014>
Download mbox | patch
Permalink /patch/90609/
State New
Headers show

Comments

Sven Krauss - April 11, 2011, 3:18 p.m.
Hello!

I am working on a TI-OMAP (OMAP3530 Kernel 2.6.33.7) board and with heavy load i got the following error. 

DMA misaligned error with device 4

BUG: soft lockup - CPU#0 stuck for 61s! [jffs2_gcd_mtd4:419]
Modules linked in:
 
Pid: 419, comm:       jffs2_gcd_mtd4
CPU: 0    Not tainted  (2.6.33.7 #1)
PC is at omap_write_buf_dma_pref+0x184/0x230
LR is at omap_write_buf_dma_pref+0x178/0x230
pc : [<c01fe170>]    lr : [<c01fe164>]    psr: 20000013
sp : cfafdc30  ip : cfafdb80  fp : cf8d2010
r10: 00000800  r9 : 00000100  r8 : c711b5be
r7 : 00000800  r6 : cf8d2000  r5 : 00000001  r4 : 00000000
r3 : fe000000  r2 : 00000001  r1 : cf8cb1c0  r0 : 00000800
Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
Control: 10c5387d  Table: 8fb40019  DAC: 00000017

From this moment the cpu is dead.

I went down to the kernel and found the following problem. I will start in jffs2_flash_writev() from fs/jffs2/wbuf.c. There is a for loop running through a vector invec. Inside the loop data is written to the write buffer (wbuf). If the buffer is full __jffs2_flush_wbuf will be called. If now an unaligned amount of data was written the next call c->mtd->write() inside the next condition will fail, because the pointer (v) is not aligned. This pointer is directly written to the dma. This results in the crash above.

I suggest the following patch. For me this works fine.

Thanks very much!

Patch

--- linux-2.6.33.7.orig/drivers/mtd/nand/omap2.c 2010-08-02 19:27:18.000000000 +0200
+++ linux-2.6.33.7/drivers/mtd/nand/omap2.c 2011-04-11 17:11:53.000000000 +0200
@@ -503,9 +506,11 @@ 
 {
  if (len <= mtd->oobsize)
  omap_write_buf_pref(mtd, buf, len);
+ else if (!IS_ALIGNED((unsigned long)buf, 4))
+ omap_write_buf_pref(mtd, buf, len);
  else
  /* start transfer in DMA mode */
- omap_nand_dma_transfer(mtd, buf, len, 0x1);
+ omap_nand_dma_transfer(mtd, (void*)buf, len, 0x1);
 }
 
 /**