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[2/2,i386] : Emit inter-unit moves using preferred_for_speed infrastructure

Message ID CAFULd4bJihALX0Cap8S3BkmiWj3VqFQ-nQhwGPdfxwSQC2NiQQ@mail.gmail.com
State New
Headers show
Series None | expand

Commit Message

Uros Bizjak April 27, 2018, 9:05 a.m. UTC 
Second part of the patch.

2018-04-27  Uros Bizjak  <ubizjak@gmail.com>

    * config/i386/i386.md (*movti_internal): Substitute Ye constraint
    with Yd constraint. Set "preferred_for_speed" attribute from
    TARGET_INTER_UNIT_MOVES_{FROM,TO}_VEC for alternatives
    with Yd constraint.
    (*movdi_internal): Ditto.
    (movti_interunit splitters): Remove
    TARGET_INTER_UNIT_MOVES_{FROM,TO}_VEC from insn condition.
    (movdi_interunit splitters): Ditto.
    * config/i386/constraints.md (Ye): Remove.
    (Yd): Do not depend on TARGET_INTER_UNIT_MOVES_{FROM,TO}_VEC.

Patch was bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.

Committed to mainline SVN.

Uros.
diff mbox series

Patch

Index: config/i386/constraints.md
===================================================================
--- config/i386/constraints.md	(revision 259682)
+++ config/i386/constraints.md	(working copy)
@@ -99,10 +99,8 @@ 
 
 ;; We use the Y prefix to denote any number of conditional register sets:
 ;;  z	First SSE register.
-;;  d	any EVEX encodable SSE register for AVX512BW target or any SSE register
-;;	for SSE4_1 target, when inter-unit moves to SSE register are enabled
-;;  e	any EVEX encodable SSE register for AVX512BW target or any SSE register
-;;	for SSE4_1 target, when inter-unit moves from SSE register are enabled
+;;  d	any EVEX encodable SSE register for AVX512BW target or
+;;	any SSE register for SSE4_1 target.
 ;;  p	Integer register when TARGET_PARTIAL_REG_STALL is disabled
 ;;  a	Integer register when zero extensions with AND are disabled
 ;;  b	Any register that can be used as the GOT base when calling
@@ -120,21 +118,9 @@ 
  "First SSE register (@code{%xmm0}).")
 
 (define_register_constraint "Yd"
- "TARGET_INTER_UNIT_MOVES_TO_VEC
-  ? (TARGET_AVX512DQ
-     ? ALL_SSE_REGS
-     : (TARGET_SSE4_1 ? SSE_REGS : NO_REGS))
-  : NO_REGS"
- "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target, when inter-unit moves to vector registers are enabled.")
+ "TARGET_AVX512DQ ? ALL_SSE_REGS : TARGET_SSE4_1 ? SSE_REGS : NO_REGS"
+ "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target.")
 
-(define_register_constraint "Ye"
- "TARGET_INTER_UNIT_MOVES_FROM_VEC
-  ? (TARGET_AVX512DQ
-     ? ALL_SSE_REGS
-     : (TARGET_SSE4_1 ? SSE_REGS : NO_REGS))
-  : NO_REGS"
- "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target, when inter-unit moves from vector registers are enabled.")
-
 (define_register_constraint "Yp"
  "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS"
  "@internal Any integer register when TARGET_PARTIAL_REG_STALL is disabled.")
Index: config/i386/i386.md
===================================================================
--- config/i386/i386.md	(revision 259682)
+++ config/i386/i386.md	(working copy)
@@ -2123,7 +2123,7 @@ 
 
 (define_insn "*movti_internal"
   [(set (match_operand:TI 0 "nonimmediate_operand" "=!r ,o ,v,v ,v ,m,?r,?Yd")
-	(match_operand:TI 1 "general_operand"	   "riFo,re,C,BC,vm,v,Ye,r"))]
+	(match_operand:TI 1 "general_operand"	   "riFo,re,C,BC,vm,v,Yd,r"))]
   "(TARGET_64BIT
     && !(MEM_P (operands[0]) && MEM_P (operands[1])))
    || (TARGET_SSE
@@ -2203,12 +2203,19 @@ 
 	       (match_test "optimize_function_for_size_p (cfun)")
 		 (const_string "V4SF")
 	       ]
-	       (const_string "TI")))])
+	       (const_string "TI")))
+   (set (attr "preferred_for_speed")
+     (cond [(eq_attr "alternative" "6")
+	      (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
+	    (eq_attr "alternative" "7")
+	      (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
+	   ]
+	   (symbol_ref "true")))])
 
 (define_split
   [(set (match_operand:TI 0 "sse_reg_operand")
         (match_operand:TI 1 "general_reg_operand"))]
-  "TARGET_64BIT && TARGET_SSE4_1 && TARGET_INTER_UNIT_MOVES_TO_VEC
+  "TARGET_64BIT && TARGET_SSE4_1
    && reload_completed"
   [(set (match_dup 2)
   	(vec_merge:V2DI
@@ -2227,7 +2234,7 @@ 
   [(set (match_operand:DI 0 "nonimmediate_operand"
     "=r  ,o  ,r,r  ,r,m ,*y,*y,?*y,?m,?r,?*y,*v,*v,*v,m ,m,?r ,?*Yd,?r,?*v,?*y,?*x,*k,*k ,*r,*m")
 	(match_operand:DI 1 "general_operand"
-    "riFo,riF,Z,rem,i,re,C ,*y,m  ,*y,*y,r  ,C ,*v,m ,*v,v,*Ye,r   ,*v,r  ,*x ,*y ,*r,*km,*k,*k"))]
+    "riFo,riF,Z,rem,i,re,C ,*y,m  ,*y,*y,r  ,C ,*v,m ,*v,v,*Yd,r   ,*v,r  ,*x ,*y ,*r,*km,*k,*k"))]
   "!(MEM_P (operands[0]) && MEM_P (operands[1]))"
 {
   switch (get_attr_type (insn))
@@ -2379,9 +2386,9 @@ 
 	   ]
 	   (const_string "DI")))
    (set (attr "preferred_for_speed")
-     (cond [(eq_attr "alternative" "10,19")
+     (cond [(eq_attr "alternative" "10,17,19")
 	      (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
-	    (eq_attr "alternative" "11,20")
+	    (eq_attr "alternative" "11,18,20")
 	      (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
 	   ]
 	   (symbol_ref "true")))
@@ -2402,7 +2409,7 @@ 
 (define_split
   [(set (match_operand:<DWI> 0 "general_reg_operand")
         (match_operand:<DWI> 1 "sse_reg_operand"))]
-  "TARGET_SSE4_1 && TARGET_INTER_UNIT_MOVES_FROM_VEC
+  "TARGET_SSE4_1
    && reload_completed"
   [(set (match_dup 2)
   	(vec_select:DWIH
@@ -2426,7 +2433,7 @@ 
 (define_split
   [(set (match_operand:DI 0 "sse_reg_operand")
         (match_operand:DI 1 "general_reg_operand"))]
-  "!TARGET_64BIT && TARGET_SSE4_1 && TARGET_INTER_UNIT_MOVES_TO_VEC
+  "!TARGET_64BIT && TARGET_SSE4_1
    && reload_completed"
   [(set (match_dup 2)
   	(vec_merge:V4SI