Patchwork [U-Boot,v8,05/10] nds32/ag101: lowlevel_init.S of ag101

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Submitter Macpaul Lin
Date April 11, 2011, 2:47 a.m.
Message ID <1302490025-22060-5-git-send-email-macpaul@andestech.com>
Download mbox | patch
Permalink /patch/90551/
State Superseded
Delegated to: Macpaul Lin
Headers show

Comments

Macpaul Lin - April 11, 2011, 2:47 a.m.
lowlevel_init.S is a peripheral initial procedure of ag101.
It configures onboard dram, clock, and power settings.
It also prepars the dram environment before moving u-boot
from rom and flash into dram.

This version of lowlevel_init.S also replace hardcode value
by MARCO defines from the GPL version andesboot for better
code quality.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
ChangeLog from v1-v4:
   - Code clean up and formatting style.

ChangeLog from v5-v6
   - Change hard code value into MARCO definitions.
   - ftsmc010
     - Fix FTSMC020_TPR_AT2 from 1 to 3 (0xff3ff)
   - ftsdmc021
     - Fix hardcoded address of CR1, CR2, TR1, TR2, BANK0 registers.
     - Fix the default configuration value of FTSDMC and FTSMC controller.
   - Remove some ftpmu010 and flash probe code to C functions.

 arch/nds32/cpu/n1213/ag101/lowlevel_init.S |  160 ++++++++++++++++++++++++++++
 1 files changed, 160 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/cpu/n1213/ag101/lowlevel_init.S

Patch

diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
new file mode 100644
index 0000000..96969ba
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
@@ -0,0 +1,160 @@ 
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+.text
+
+#include <common.h>
+#include <config.h>
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+.globl	lowlevel_init
+lowlevel_init:
+	move	$r10, $lp
+	jal	mem_init
+	jal	remap
+
+	ret	$r10
+
+mem_init:
+	move	$r11, $lp
+
+	/*
+	 * mem_init:
+	 *	There are 2 bank connected to FTSMC020 on AG101
+	 *	BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
+	 *	we need to set onboard SDRAM before remap and relocation.
+	 */
+	li	$r0, (CONFIG_FTSMC020_BASE+FTSMC020_BANK0_CR)
+	li	$r1, (FTSMC020_BANK1_CONFIG)			! 0x10000052
+	swi	$r1, [$r0]
+	li	$r1, (FTSMC020_BANK1_TIMING)			! 0x00151151
+	swi	$r1, [$r0+FTSMC020_BANK0_TPR]
+
+	/*
+	 * config AHB Controller
+	 */
+	li	$r0, (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
+	li	$r1, (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6)
+	swi	$r1, [$r0]
+
+	/*
+	 * config PMU
+	 */
+	li	$r0, (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
+	lwi	$r1, [$r0]
+	! ftpmu010_dlldis_disable, must do it in lowleve_init
+	li	$r2, FTPMU010_PDLLCR0_DLLDIS			! 0x00010000
+	or	$r1, $r1, $r2
+	swi	$r1, [$r0]
+
+	/*
+	 * config SDRAM controller
+	 */
+	li	$r0, (CONFIG_FTSDMC021_BASE)
+	li	$r1, (CONFIG_SYS_FTSDMC021_TP1) ! 0x00011312
+	swi	$r1, [$r0]
+	li	$r1, (CONFIG_SYS_FTSDMC021_TP2) ! 0x00480180
+	swi	$r1, [$r0+FTSDMC021_OFFSET_TP2]
+	li	$r1, (CONFIG_SYS_FTSDMC021_CR1)	! 0x00002326
+	swi	$r1, [$r0+FTSDMC021_OFFSET_CR1]
+	li	$r1, (FTSDMC021_CR2_IPREC)	! 0x00000010
+	swi	$r1, [$r0+FTSDMC021_OFFSET_CR2]
+1:
+	lwi	$r1, [$r0+FTSDMC021_OFFSET_CR2]
+	andi	$r1, $r1, (CONFIG_SYS_FTSDMC021_CR2)	! 0x1C
+	bnez	$r1, 1b
+
+	li	$r1, (FTSDMC021_CR2_ISMR)	! 0x00000004
+	swi	$r1, [$r0+FTSDMC021_OFFSET_CR2]
+2:
+	lwi	$r1, [$r0+FTSDMC021_OFFSET_CR2]
+	bnez	$r1, 2b
+
+	li	$r1, (FTSDMC021_CR2_IREF)	! 0x00000008
+	swi	$r1, [$r0+FTSDMC021_OFFSET_CR2]
+3:
+	lwi	$r1, [$r0+FTSDMC021_OFFSET_CR2]
+	bnez	$r1, 3b
+
+	move	$lp, $r11
+	ret
+
+remap:
+	move	$r11, $lp
+#ifdef __NDS32_N1213_43U1H__	/* AG101 */
+	bal	2f
+relo_base:
+	move	$r0, $lp
+#else
+relo_base:
+	mfusr	$r0, $pc
+#endif
+
+	/*
+	 * relocation, copy ROM code to SDRAM (current at 0x10000000)
+	 */
+	li	$r4, CONFIG_SYS_RELO_ADDR		! 0x10000000
+	li	$r5, 0x0
+	la	$r1, relo_base
+	sub	$r2, $r0, $r1
+	sethi	$r6, hi20(andesboot_end)
+	ori	$r6, $r6, lo12(andesboot_end)
+	add	$r6, $r6, $r2
+1:
+	lwi	$r7, [$r5]
+	swi	$r7, [$r4]
+	addi	$r5, $r5, #4
+	addi	$r4, $r4, #4
+	blt	$r5, $r6, 1b
+
+	/*
+	 * Remapping
+	 */
+	li	$r0, (CONFIG_FTSDMC021_BASE + FTSDMC021_OFFSET_TP1)
+	li	$r1, (CONFIG_SYS_FTSDMC021_BANK0_BSR)	! 0x00001100
+	swi	$r1, [$r0+FTSDMC021_OFFSET_BANK0_BSR]
+	li	$r1, 0x0
+	swi	$r1, [$r0+FTSDMC021_OFFSET_BANK1_BSR]
+	swi	$r1, [$r0+FTSDMC021_OFFSET_BANK2_BSR]
+	swi	$r1, [$r0+FTSDMC021_OFFSET_BANK3_BSR]
+	li	$r1, (FTSDMC021_BANK_ENABLE)		! 0x00001000
+	swi	$r1, [$r0+FTSDMC021_OFFSET_BANK0_BSR]
+
+	li	$r0, (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
+	lwi	$r1, [$r0]
+	ori	$r1, $r1, FTAHBC020S_CR_REMAP		! 0x1
+	swi	$r1, [$r0]
+
+	li	$r0, (CONFIG_FTSMC020_BASE)
+
+	move	$lp, $r11
+2:
+	ret
+
+.globl show_led
+show_led:
+    li      $r8, (CONFIG_DEBUG_LED)
+    swi     $r7, [$r8]
+    ret
+#endif