From patchwork Fri Apr 27 02:55:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 905483 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40XJV10d5Kz9s0v for ; Fri, 27 Apr 2018 12:56:09 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=jms.id.au Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="k3KhfW2h"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 40XJV03b8GzF265 for ; Fri, 27 Apr 2018 12:56:08 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=jms.id.au Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="k3KhfW2h"; dkim-atps=neutral X-Original-To: linux-aspeed@lists.ozlabs.org Delivered-To: linux-aspeed@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c00::244; helo=mail-pf0-x244.google.com; envelope-from=joel.stan@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=jms.id.au Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="k3KhfW2h"; dkim-atps=neutral Received: from mail-pf0-x244.google.com (mail-pf0-x244.google.com [IPv6:2607:f8b0:400e:c00::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 40XJTt3hnvzF24D for ; Fri, 27 Apr 2018 12:56:01 +1000 (AEST) Received: by mail-pf0-x244.google.com with SMTP id f189so369810pfa.7 for ; Thu, 26 Apr 2018 19:56:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=lLaYir9fo/gzqpZV3NgYIW7bx4xHltOLwyg7NLUydss=; b=k3KhfW2hUnmc04T61zEynKks6C7vidLncbRiBt+vtYK8veWaXn5VLFBseh7iB1vF8p vb2jK4Vi9xz0XMUa6LtUFlLkw+c+0jnOlEYxQy89O7GzS75rh6Ues8JImXt5cxw4AGAM ammw1X3sfhRHIOPe9vAK93ZAuHI9o4jWvABp773HQ/9ZVBzVQbbe4SYfIwxBod1mPSa1 WSaMh8qrot44X9YHu/GEgy2kfvEL6YaxQ9Or4nSqnu4RGDfJf9FyQp7ineB3MKrOzBWR UxH5saIrKoBdXT9Hc2bmu7KOkMaJjGnSFFqkrMyUH2f0wtxYeCLzZTNczvfeSOH2LOXz eqhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=lLaYir9fo/gzqpZV3NgYIW7bx4xHltOLwyg7NLUydss=; b=OfnYJhJBzRvFWYJbQFJ/jNr5UQJDDhwmrvcaN9TK2v+THrWc2aNQ8E/mvkE3pYYOPc hUfhyPsH14KDVjw+pz0uYi71Me9PIexmL29mzlop1owyNMva1coqzWtZPGOU7BwuTjiR ToIvHQ+pom0hOJ2ztf9LhDinN/FAq9MXcjmXeC9bKZ0v9VsLlJdfDmh1O7jzBLVb4L5j qLU/gXc+PmkeKymfQy1P4BfLuog3+nU9bUJRd4RhOf4CII66rDV1/vINjs7ws0mYfgnX K/MQQoc7H3hIA4oH1hurofQf5VKE50TkY8eNvOplQU6oUzU4w9d8GtmI93zahgSKPiBf 9vjg== X-Gm-Message-State: ALQs6tD9rWNMRpLSUXm47KrmrpXoYUDeUJZMLaCWExv4IRfndmjzfQ6E MZwax2LDVYYgoUJpuDP7VuY= X-Google-Smtp-Source: AB8JxZpfpti6pQoaAYEcFD5K74jakg9qIyK4gDn94XdY/WpKdmV3k5feGutEF7OHEgbR85kJzi8WFQ== X-Received: by 2002:a65:600a:: with SMTP id m10-v6mr522072pgu.281.1524797759495; Thu, 26 Apr 2018 19:55:59 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id h1-v6sm299609pgf.93.2018.04.26.19.55.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 26 Apr 2018 19:55:58 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Fri, 27 Apr 2018 12:25:50 +0930 From: Joel Stanley To: Michael Turquette , Stephen Boyd Subject: [PATCH v2] clk: aspeed: Support second reset register Date: Fri, 27 Apr 2018 12:25:47 +0930 Message-Id: <20180427025547.14115-1-joel@jms.id.au> X-Mailer: git-send-email 2.17.0 X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jae Hyun Yoo , Ryan Chen , linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" The ast2500 has an additional reset register that contains resets not present in the ast2400. This enables support for this register, and adds the one reset line that is controlled by it. Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- v2: This commit fixes a bug in aspeed_reset_assert() which determines the second reset register using condition. drivers/clk/clk-aspeed.c | 44 +++++++++++++++++++----- include/dt-bindings/clock/aspeed-clock.h | 1 + 2 files changed, 37 insertions(+), 8 deletions(-) diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index c7cb1f2b6f8a..1fbf45738535 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -16,6 +16,8 @@ #define ASPEED_NUM_CLKS 35 +#define ASPEED_RESET2_OFFSET 32 + #define ASPEED_RESET_CTRL 0x04 #define ASPEED_CLK_SELECTION 0x08 #define ASPEED_CLK_STOP_CTRL 0x0c @@ -30,6 +32,7 @@ #define CLKIN_25MHZ_EN BIT(23) #define AST2400_CLK_SOURCE_SEL BIT(18) #define ASPEED_CLK_SELECTION_2 0xd8 +#define ASPEED_RESET_CTRL2 0xd4 /* Globally visible clocks */ static DEFINE_SPINLOCK(aspeed_clk_lock); @@ -291,6 +294,7 @@ struct aspeed_reset { #define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev) static const u8 aspeed_resets[] = { + /* SCU04 resets */ [ASPEED_RESET_XDMA] = 25, [ASPEED_RESET_MCTP] = 24, [ASPEED_RESET_ADC] = 23, @@ -300,38 +304,62 @@ static const u8 aspeed_resets[] = { [ASPEED_RESET_PCIVGA] = 8, [ASPEED_RESET_I2C] = 2, [ASPEED_RESET_AHB] = 1, + + /* + * SCUD4 resets start at an offset to separate them from + * the SCU04 resets. + */ + [ASPEED_RESET_CRT1] = ASPEED_RESET2_OFFSET + 5, }; static int aspeed_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) { struct aspeed_reset *ar = to_aspeed_reset(rcdev); - u32 rst = BIT(aspeed_resets[id]); + u32 reg = ASPEED_RESET_CTRL; + u32 bit = aspeed_resets[id]; + + if (bit >= ASPEED_RESET2_OFFSET) { + bit -= ASPEED_RESET2_OFFSET; + reg = ASPEED_RESET_CTRL2; + } - return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, 0); + return regmap_update_bits(ar->map, reg, BIT(bit), 0); } static int aspeed_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) { struct aspeed_reset *ar = to_aspeed_reset(rcdev); - u32 rst = BIT(aspeed_resets[id]); + u32 reg = ASPEED_RESET_CTRL; + u32 bit = aspeed_resets[id]; - return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, rst); + if (bit >= ASPEED_RESET2_OFFSET) { + bit -= ASPEED_RESET2_OFFSET; + reg = ASPEED_RESET_CTRL2; + } + + return regmap_update_bits(ar->map, reg, BIT(bit), BIT(bit)); } static int aspeed_reset_status(struct reset_controller_dev *rcdev, unsigned long id) { struct aspeed_reset *ar = to_aspeed_reset(rcdev); - u32 val, rst = BIT(aspeed_resets[id]); - int ret; + u32 reg = ASPEED_RESET_CTRL; + u32 bit = aspeed_resets[id]; + int ret, val; + + if (bit >= ASPEED_RESET2_OFFSET) { + bit -= ASPEED_RESET2_OFFSET; + reg = ASPEED_RESET_CTRL2; + } - ret = regmap_read(ar->map, ASPEED_RESET_CTRL, &val); + ret = regmap_read(ar->map, reg, &val); if (ret) return ret; - return !!(val & rst); + return !!(val & BIT(bit)); } static const struct reset_control_ops aspeed_reset_ops = { diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index d3558d897a4d..513c1b4af7a8 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -48,5 +48,6 @@ #define ASPEED_RESET_PCIVGA 6 #define ASPEED_RESET_I2C 7 #define ASPEED_RESET_AHB 8 +#define ASPEED_RESET_CRT1 9 #endif