From patchwork Sat Apr 9 18:05:35 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefano Babic X-Patchwork-Id: 90480 X-Patchwork-Delegate: s-paulraj@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 82E11B6F15 for ; Sun, 10 Apr 2011 04:07:24 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9669D2812C; Sat, 9 Apr 2011 20:07:10 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Qt0ag1hpzz2d; Sat, 9 Apr 2011 20:07:10 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CA25E2812D; Sat, 9 Apr 2011 20:06:54 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 500542810B for ; Sat, 9 Apr 2011 20:06:53 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id zyFJ+KUqcb0G for ; Sat, 9 Apr 2011 20:06:52 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from smtpi4.ngi.it (smtpi4.ngi.it [88.149.128.104]) by theia.denx.de (Postfix) with ESMTP id 7D06F280F6 for ; Sat, 9 Apr 2011 20:06:44 +0200 (CEST) Received: from paperina.lan (unknown [88.149.182.160]) by smtpi4.ngi.it (Postfix) with ESMTP id 1AB90421F3; Sat, 9 Apr 2011 20:06:41 +0200 (CEST) Received: from papero.lan (papero.lan [192.168.2.105]) by paperina.lan (Postfix) with ESMTP id 2918D140A0FC; Sat, 9 Apr 2011 20:06:41 +0200 (CEST) From: Stefano Babic To: u-boot@lists.denx.de Date: Sat, 9 Apr 2011 20:05:35 +0200 Message-Id: <1302372335-30232-6-git-send-email-sbabic@denx.de> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1302372335-30232-1-git-send-email-sbabic@denx.de> References: <1302372335-30232-1-git-send-email-sbabic@denx.de> Cc: Scott Wood Subject: [U-Boot] [PATCH 6/6] EA20: do not use subpage write for NAND X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The NAND controller does not support subpage accessing. This is not used at all for MLC NAND, but it is set for SLC NAND. UBI tries to access to subpages, and because it fails, it starts "torture tests" on the whole page that are always successful, making an endless loop with the UBI background task taking most CPU time. On the console, the issue is recognized by the messages: UBI error: ubi_io_read: error -74 (ECC error) while reading 512 bytes from PEB 37:512, read 512 bytes UBI: run torture test for PEB 37 UBI: PEB 37 passed torture test, do not mark it a bad Signed-off-by: Stefano Babic CC: Ben Gardiner CC: Sandeep Paulraj CC: Scott Wood --- README | 4 ++++ drivers/mtd/nand/davinci_nand.c | 3 +++ include/configs/ea20.h | 1 + include/linux/mtd/nand.h | 3 ++- 4 files changed, 10 insertions(+), 1 deletions(-) diff --git a/README b/README index 21cd71b..8d664eb 100644 --- a/README +++ b/README @@ -2907,6 +2907,10 @@ Low Level (hardware related) configuration options: that is executed before the actual U-Boot. E.g. when compiling a NAND SPL. +- CONFIG_SYS_NAND_NO_SUBPAGE + Some drivers (davinci) do not support access to NAND subpage. + + Building the Software: ====================== diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index d41579c..f6c7d09 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -609,6 +609,9 @@ void davinci_nand_init(struct nand_chip *nand) #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT nand->options |= NAND_USE_FLASH_BBT; #endif +#ifdef CONFIG_SYS_NAND_NO_SUBPAGE + nand->options |= NAND_NO_SUBPAGE_WRITE; +#endif #ifdef CONFIG_SYS_NAND_HW_ECC nand->ecc.mode = NAND_ECC_HW; nand->ecc.size = 512; diff --git a/include/configs/ea20.h b/include/configs/ea20.h index 1843dae..9e5dda4 100644 --- a/include/configs/ea20.h +++ b/include/configs/ea20.h @@ -171,6 +171,7 @@ #define CONFIG_NAND_DAVINCI #define CONFIG_SYS_NAND_PAGE_2K +#define CONFIG_SYS_NAND_NO_SUBPAGE #define CONFIG_SYS_NAND_CS 2 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE #undef CONFIG_SYS_NAND_HW_ECC diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 987a2ec..215e781 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -193,7 +193,8 @@ typedef enum { && (chip->page_shift > 9)) /* Mask to zero out the chip options, which come from the id table */ -#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR) +#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR & \ + ~NAND_NO_SUBPAGE_WRITE) /* Non chip related options */ /* Use a flash based bad block table. This option is passed to the