diff mbox series

[v8,02/35] RISC-V: Make virt board description match spike

Message ID	1524699938-6764-3-git-send-email-mjc@sifive.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Michael Clark <mjc@sifive.com> To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:45:05 +1200 Message-Id: <1524699938-6764-3-git-send-email-mjc@sifive.com> In-Reply-To: <1524699938-6764-1-git-send-email-mjc@sifive.com> References: <1524699938-6764-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v8 02/35] RISC-V: Make virt board description match spike Precedence: list Cc: patches@groups.riscv.org, Michael Clark <mjc@sifive.com>, Palmer Dabbelt <palmer@sifive.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	QEMU 2.13 Privileged ISA emulation updates \| expand [v8,00/35] QEMU 2.13 Privileged ISA emulation updates [v8,01/35] RISC-V: Replace hardcoded constants with enum values [v8,02/35] RISC-V: Make virt board description match spike [v8,03/35] RISC-V: Use ROM base address and size from memmap [v8,04/35] RISC-V: Remove identity_translate from load_elf [v8,05/35] RISC-V: Remove unused class definitions [v8,06/35] RISC-V: Include instruction hex in disassembly [v8,07/35] RISC-V: Make some header guards more specific [v8,08/35] RISC-V: Make virt header comment title consistent [v8,09/35] RISC-V: Remove EM_RISCV ELF_MACHINE indirection [v8,10/35] RISC-V: Remove erroneous comment from translate.c [v8,11/35] RISC-V: Mark ROM read-only after copying in code [v8,12/35] RISC-V: Update address bits to support sv39 and sv48 [v8,13/35] RISC-V: Improve page table walker spec compliance [v8,14/35] RISC-V: Update E order and I extension order [v8,15/35] RISC-V: Hardwire satp to 0 for no-mmu case [v8,16/35] RISC-V: Make mtvec/stvec ignore vectored traps [v8,17/35] RISC-V: No traps on writes to misa, minstret, mcycle [v8,18/35] RISC-V: Clear mtval/stval on exceptions without info [v8,19/35] RISC-V: Allow S-mode mxr access when priv ISA >= v1.10 [v8,20/35] RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10 [v8,21/35] RISC-V: Add mcycle/minstret support for -icount auto [v8,22/35] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps [v8,23/35] RISC-V: Simplify riscv_cpu_local_irqs_pending [v8,24/35] RISC-V: Allow setting and clearing multiple irqs [v8,25/35] RISC-V: Move non-ops from op_helper to cpu_helper [v8,26/35] RISC-V: Update CSR and interrupt definitions [v8,27/35] RISC-V: Implement modular CSR helper interface [v8,28/35] RISC-V: Implement atomic mip/sip CSR updates [v8,29/35] RISC-V: Implement existential predicates for CSRs [v8,30/35] RISC-V: Split out mstatus_fs from tb_flags [v8,31/35] RISC-V: Mark mstatus.fs dirty [v8,32/35] RISC-V: Implement mstatus.TSR/TW/TVM [v8,33/35] RISC-V: Add public API for the CSR dispatch table [v8,34/35] RISC-V: Add hartid and \n to interrupt logging [v8,35/35] RISC-V: Use riscv prefix consistently on cpu helpers

Commit Message

Michael Clark April 25, 2018, 11:45 p.m. UTC

This makes 'qemu-system-riscv64 -machine help' output more tidy
and consistent.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 hw/riscv/virt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 86a86c9..dc74fd6 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -407,7 +407,7 @@  static const TypeInfo riscv_virt_board_device = {
 
 static void riscv_virt_board_machine_init(MachineClass *mc)
 {
-    mc->desc = "RISC-V VirtIO Board (Privileged spec v1.10)";
+    mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)";
     mc->init = riscv_virt_board_init;
     mc->max_cpus = 8; /* hardcoded limit in BBL */
 }