Patchwork [U-Boot,04/30] powerpc/km82xx: cleanup coding style for mgcoge.c

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Submitter Valentin Longchamp
Date April 8, 2011, 2:23 p.m.
Message ID <c8fbb1b3e75aecd217433b35ac6a7cefd93ea9a7.1302272395.git.valentin.longchamp@keymile.com>
Download mbox | patch
Permalink /patch/90356/
State Superseded
Headers show

Comments

Valentin Longchamp - April 8, 2011, 2:23 p.m.
From: Holger Brunck <holger.brunck@keymile.com>

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Acked-by: Heiko Schocher <hs@denx.de>
cc: Wolfgang Denk <wd@denx.de>
cc: Detlev Zundel <dzu@denx.de>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
---
 board/keymile/mgcoge/mgcoge.c |  291 +++++++++++++++++++++--------------------
 1 files changed, 146 insertions(+), 145 deletions(-)

Patch

diff --git a/board/keymile/mgcoge/mgcoge.c b/board/keymile/mgcoge/mgcoge.c
index 11a0f79..3db3c7b 100644
--- a/board/keymile/mgcoge/mgcoge.c
+++ b/board/keymile/mgcoge/mgcoge.c
@@ -45,154 +45,154 @@ 
  */
 const iop_conf_t iop_conf_tab[4][32] = {
 
-    /* Port A */
-    {	/*	      conf	ppar psor pdir podr pdat */
-	/* PA31 */ { 0,		 0,   0,   0,	0,   0 }, /* PA31	     */
-	/* PA30 */ { 0,		 0,   0,   0,	0,   0 }, /* PA30	     */
-	/* PA29 */ { 0,		 0,   0,   0,	0,   0 }, /* PA29	     */
-	/* PA28 */ { 0,		 0,   0,   0,	0,   0 }, /* PA28	     */
-	/* PA27 */ { 0,		 0,   0,   0,	0,   0 }, /* PA27	     */
-	/* PA26 */ { 0,		 0,   0,   0,	0,   0 }, /* PA26	     */
-	/* PA25 */ { 0,		 0,   0,   0,	0,   0 }, /* PA25	     */
-	/* PA24 */ { 0,		 0,   0,   0,	0,   0 }, /* PA24	     */
-	/* PA23 */ { 0,		 0,   0,   0,	0,   0 }, /* PA23	     */
-	/* PA22 */ { 0,		 0,   0,   0,	0,   0 }, /* PA22	     */
-	/* PA21 */ { 0,		 0,   0,   0,	0,   0 }, /* PA21	     */
-	/* PA20 */ { 0,		 0,   0,   0,	0,   0 }, /* PA20	     */
-	/* PA19 */ { 0,		 0,   0,   0,	0,   0 }, /* PA19	     */
-	/* PA18 */ { 0,		 0,   0,   0,	0,   0 }, /* PA18	     */
-	/* PA17 */ { 0,		 0,   0,   0,	0,   0 }, /* PA17	     */
-	/* PA16 */ { 0,		 0,   0,   0,	0,   0 }, /* PA16	     */
-	/* PA15 */ { 0,		 0,   0,   0,	0,   0 }, /* PA15	     */
-	/* PA14 */ { 0,		 0,   0,   0,	0,   0 }, /* PA14	     */
-	/* PA13 */ { 0,		 0,   0,   0,	0,   0 }, /* PA13	     */
-	/* PA12 */ { 0,		 0,   0,   0,	0,   0 }, /* PA12	     */
-	/* PA11 */ { 0,		 0,   0,   0,	0,   0 }, /* PA11	     */
-	/* PA10 */ { 0,		 0,   0,   0,	0,   0 }, /* PA10	     */
-	/* PA9	*/ { 1,		 1,   0,   1,	0,   0 }, /* SMC2 TxD	     */
-	/* PA8	*/ { 1,		 1,   0,   0,	0,   0 }, /* SMC2 RxD	     */
-	/* PA7	*/ { 0,		 0,   0,   0,	0,   0 }, /* PA7	     */
-	/* PA6	*/ { 0,		 0,   0,   0,	0,   0 }, /* PA6	     */
-	/* PA5	*/ { 0,		 0,   0,   0,	0,   0 }, /* PA5	     */
-	/* PA4	*/ { 0,		 0,   0,   0,	0,   0 }, /* PA4	     */
-	/* PA3	*/ { 0,		 0,   0,   0,	0,   0 }, /* PA3	     */
-	/* PA2	*/ { 0,		 0,   0,   0,	0,   0 }, /* PA2	     */
-	/* PA1	*/ { 0,		 0,   0,   0,	0,   0 }, /* PA1	     */
-	/* PA0	*/ { 0,		 0,   0,   0,	0,   0 }  /* PA0	     */
-    },
-
-    /* Port B */
-    {	/*	      conf	ppar psor pdir podr pdat */
-	/* PB31 */ { 0,		 0,   0,   0,	0,   0 }, /* PB31	     */
-	/* PB30 */ { 0,		 0,   0,   0,	0,   0 }, /* PB30	     */
-	/* PB29 */ { 0,		 0,   0,   0,	0,   0 }, /* PB29	     */
-	/* PB28 */ { 0,		 0,   0,   0,	0,   0 }, /* PB28	     */
-	/* PB27 */ { 0,		 0,   0,   0,	0,   0 }, /* PB27	     */
-	/* PB26 */ { 0,		 0,   0,   0,	0,   0 }, /* PB26	     */
-	/* PB25 */ { 0,		 0,   0,   0,	0,   0 }, /* PB25	     */
-	/* PB24 */ { 0,		 0,   0,   0,	0,   0 }, /* PB24	     */
-	/* PB23 */ { 0,		 0,   0,   0,	0,   0 }, /* PB23	     */
-	/* PB22 */ { 0,		 0,   0,   0,	0,   0 }, /* PB22	     */
-	/* PB21 */ { 0,		 0,   0,   0,	0,   0 }, /* PB21	     */
-	/* PB20 */ { 0,		 0,   0,   0,	0,   0 }, /* PB20	     */
-	/* PB19 */ { 0,		 0,   0,   0,	0,   0 }, /* PB19	     */
-	/* PB18 */ { 0,		 0,   0,   0,	0,   0 }, /* PB18	     */
-	/* PB17 */ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-	/* PB16 */ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-	/* PB15 */ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-	/* PB14 */ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-	/* PB13 */ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-	/* PB12 */ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-	/* PB11 */ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-	/* PB10 */ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-	/* PB9	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-	/* PB8	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-	/* PB7	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-	/* PB6	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-	/* PB5	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-	/* PB4	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-	/* PB3	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-	/* PB2	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-	/* PB1	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-	/* PB0	*/ { 0,		 0,   0,   0,	0,   0 }  /* non-existent    */
-    },
-
-    /* Port C */
-    {	/*	      conf	ppar psor pdir podr pdat */
-	/* PC31 */ { 0,		 0,   0,   0,	0,   0 }, /* PC31	     */
-	/* PC30 */ { 0,		 0,   0,   0,	0,   0 }, /* PC30	     */
-	/* PC29 */ { 0,		 0,   0,   0,	0,   0 }, /* PC29	     */
-	/* PC28 */ { 0,		 0,   0,   0,	0,   0 }, /* PC28	     */
-	/* PC27 */ { 0,		 0,   0,   0,	0,   0 }, /* PC27	     */
-	/* PC26 */ { 0,		 0,   0,   0,	0,   0 }, /* PC26	     */
-	/* PC25 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC4 RxClk      */
-	/* PC24 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC4 TxClk      */
-	/* PC23 */ { 0,		 0,   0,   0,	0,   0 }, /* PC23	     */
-	/* PC22 */ { 0,		 0,   0,   0,	0,   0 }, /* PC22	     */
-	/* PC21 */ { 0,		 0,   0,   0,	0,   0 }, /* PC21	     */
-	/* PC20 */ { 0,		 0,   0,   0,	0,   0 }, /* PC20	     */
-	/* PC19 */ { 0,		 0,   0,   0,	0,   0 }, /* PC19	     */
-	/* PC18 */ { 0,		 0,   0,   0,	0,   0 }, /* PC18	     */
-	/* PC17 */ { 0,		 0,   0,   0,	0,   0 }, /* PC17	     */
-	/* PC16 */ { 0,		 0,   0,   0,	0,   0 }, /* PC16	     */
-	/* PC15 */ { 0,		 0,   0,   0,	0,   0 }, /* PC15	     */
-	/* PC14 */ { 0,		 0,   0,   0,	0,   0 }, /* PC14	     */
-	/* PC13 */ { 0,		 0,   0,   0,	0,   0 }, /* PC13	     */
-	/* PC12 */ { 0,		 0,   0,   0,	0,   0 }, /* PC12	     */
-	/* PC11 */ { 0,		 0,   0,   0,	0,   0 }, /* PC11	     */
-	/* PC10 */ { 0,		 0,   0,   0,	0,   0 }, /* PC10	     */
-	/* PC9	*/ { 1,		 1,   0,   0,	0,   0 }, /* SCC4: CTS	     */
-	/* PC8	*/ { 1,		 1,   0,   0,	0,   0 }, /* SCC4: CD	     */
-	/* PC7	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC7	     */
-	/* PC6	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC6	     */
-	/* PC5	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC5	     */
-	/* PC4	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC4	     */
-	/* PC3	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC3	     */
-	/* PC2	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC2	     */
-	/* PC1	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC1	     */
-	/* PC0	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC0	     */
-    },
-
-    /* Port D */
-    {	/*	      conf	ppar psor pdir podr pdat */
-	/* PD31 */ { 0,		 0,   0,   0,	0,   0 }, /* PD31	     */
-	/* PD30 */ { 0,		 0,   0,   0,	0,   0 }, /* PD30	     */
-	/* PD29 */ { 0,		 0,   0,   0,	0,   0 }, /* PD29	     */
-	/* PD28 */ { 0,		 0,   0,   0,	0,   0 }, /* PD28	     */
-	/* PD27 */ { 0,		 0,   0,   0,	0,   0 }, /* PD27	     */
-	/* PD26 */ { 0,		 0,   0,   0,	0,   0 }, /* PD26	     */
-	/* PD25 */ { 0,		 0,   0,   0,	0,   0 }, /* PD25	     */
-	/* PD24 */ { 0,		 0,   0,   0,	0,   0 }, /* PD24	     */
-	/* PD23 */ { 0,		 0,   0,   0,	0,   0 }, /* PD23	     */
-	/* PD22 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC4: RXD	     */
-	/* PD21 */ { 1,		 1,   0,   1,	0,   0 }, /* SCC4: TXD	     */
-	/* PD20 */ { 1,		 1,   0,   1,	0,   0 }, /* SCC4: RTS	     */
-	/* PD19 */ { 0,		 0,   0,   0,	0,   0 }, /* PD19	     */
-	/* PD18 */ { 0,		 0,   0,   0,	0,   0 }, /* PD18	     */
-	/* PD17 */ { 0,		 0,   0,   0,	0,   0 }, /* PD17	     */
-	/* PD16 */ { 0,		 0,   0,   0,	0,   0 }, /* PD16	     */
+	/* Port A */
+	{	/*	      conf	ppar psor pdir podr pdat */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA31	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA30	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA29	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA28	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA27	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA26	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA25	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA24	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA23	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA22	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA21	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA20	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA19	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA18	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA17	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA16	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA15	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA14	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA13	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA12	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA11	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA10	     */
+		{ 1,		 1,   0,   1,	0,   0 }, /* PA9 SMC2 TxD    */
+		{ 1,		 1,   0,   0,	0,   0 }, /* PA8 SMC2 RxD    */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA7	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA6	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA5	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA4	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA3	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA2	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PA1	     */
+		{ 0,		 0,   0,   0,	0,   0 }  /* PA0	     */
+	},
+
+	/* Port B */
+	{	/*	      conf	ppar psor pdir podr pdat */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PB31	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PB30	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PB29	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PB28	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PB27	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PB26	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PB25	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PB24	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PB23	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PB22	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PB21	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PB20	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PB19	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PB18	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+		{ 0,		 0,   0,   0,	0,   0 }  /* non-existent    */
+	},
+
+	/* Port C */
+	{	/*	      conf	ppar psor pdir podr pdat */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC31	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC30	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC29	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC28	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC27	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC26	     */
+		{ 1,		 1,   0,   0,	0,   0 }, /* PC25 RxClk      */
+		{ 1,		 1,   0,   0,	0,   0 }, /* PC24 TxClk      */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC23	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC22	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC21	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC20	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC19	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC18	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC17	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC16	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC15	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC14	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC13	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC12	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC11	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC10	     */
+		{ 1,		 1,   0,   0,	0,   0 }, /* PC9  SCC4: CTS  */
+		{ 1,		 1,   0,   0,	0,   0 }, /* PC8  SCC4: CD   */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC7	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC6	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC5	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC4	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC3	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC2	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC1	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PC0	     */
+	},
+
+	/* Port D */
+	{	/*	      conf	ppar psor pdir podr pdat */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PD31	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PD30	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PD29	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PD28	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PD27	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PD26	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PD25	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PD24	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PD23	     */
+		{ 1,		 1,   0,   0,	0,   0 }, /* PD22 SCC4: RXD  */
+		{ 1,		 1,   0,   1,	0,   0 }, /* PD21 SCC4: TXD  */
+		{ 1,		 1,   0,   1,	0,   0 }, /* PD20 SCC4: RTS  */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PD19	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PD18	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PD17	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PD16	     */
 #if defined(CONFIG_HARD_I2C)
-	/* PD15 */ { 1,		 1,   1,   0,	1,   0 }, /* I2C SDA	     */
-	/* PD14 */ { 1,		 1,   1,   0,	1,   0 }, /* I2C SCL	     */
+		{ 1,		 1,   1,   0,	1,   0 }, /* PD15 I2C SDA    */
+		{ 1,		 1,   1,   0,	1,   0 }, /* PD14 I2C SCL    */
 #else
-	/* PD15 */ { 1,		 0,   0,   0,	1,   1 }, /* PD15	     */
-	/* PD14 */ { 1,		 0,   0,   1,	1,   1 }, /* PD14	     */
+		{ 1,		 0,   0,   0,	1,   1 }, /* PD15	     */
+		{ 1,		 0,   0,   1,	1,   1 }, /* PD14	     */
 #endif
-	/* PD13 */ { 0,		 0,   0,   0,	0,   0 }, /* PD13	     */
-	/* PD12 */ { 0,		 0,   0,   0,	0,   0 }, /* PD12	     */
-	/* PD11 */ { 0,		 0,   0,   0,	0,   0 }, /* PD11	     */
-	/* PD10 */ { 0,		 0,   0,   0,	0,   0 }, /* PD10	     */
-	/* PD9	*/ { 0,		 0,   0,   0,	0,   0 }, /* PD9	     */
-	/* PD8	*/ { 0,		 0,   0,   0,	0,   0 }, /* PD8	     */
-	/* PD7	*/ { 0,		 0,   0,   0,	0,   0 }, /* PD7	     */
-	/* PD6	*/ { 0,		 0,   0,   0,	0,   0 }, /* PD6	     */
-	/* PD5	*/ { 0,		 0,   0,   0,	0,   0 }, /* PD5	     */
-	/* PD4	*/ { 0,		 0,   0,   0,	0,   0 }, /* PD4	     */
-	/* PD3	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-	/* PD2	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-	/* PD1	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-	/* PD0	*/ { 0,		 0,   0,   0,	0,   0 }  /* non-existent    */
-    }
+		{ 0,		 0,   0,   0,	0,   0 }, /* PD13	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PD12	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PD11	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PD10	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PD9	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PD8	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PD7	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PD6	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PD5	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* PD4	     */
+		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+		{ 0,		 0,   0,   0,	0,   0 }  /* non-existent    */
+	}
 };
 
 /*
@@ -237,7 +237,8 @@  static long int try_init(memctl8260_t *memctl, ulong sdmr,
 	 *  accessing the SDRAM with a single-byte transaction."
 	 *
 	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+	 * get here. The SDRAM can be accessed at the address
+	 * CONFIG_SYS_SDRAM_BASE.
 	 */
 
 	out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_PREA);
@@ -257,7 +258,7 @@  static long int try_init(memctl8260_t *memctl, ulong sdmr,
 	size = get_ram_size((long *)base, maxsize);
 	out_be32(&memctl->memc_or1, orx | ~(size - 1));
 
-	return (size);
+	return size;
 }
 
 phys_size_t initdram(int board_type)
@@ -279,7 +280,7 @@  phys_size_t initdram(int board_type)
 
 	icache_enable();
 
-	return (psize);
+	return psize;
 }
 
 int checkboard(void)