[RFC,12/16] powerpc/xive: update HW definitions

Message ID 20180423164341.15767-13-clg@kaod.org
State RFC
Headers show
Series
  • KVM: PPC: Book3S HV: add XIVE native exploitation mode
Related show

Commit Message

Cédric Le Goater April 23, 2018, 4:43 p.m.
We will need some of the XIVE internal structure definitions for
migration.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 arch/powerpc/include/asm/xive-regs.h | 45 ++++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

Patch

diff --git a/arch/powerpc/include/asm/xive-regs.h b/arch/powerpc/include/asm/xive-regs.h
index fa4288822b68..f1d398a48a3b 100644
--- a/arch/powerpc/include/asm/xive-regs.h
+++ b/arch/powerpc/include/asm/xive-regs.h
@@ -123,6 +123,51 @@ 
 #define TM_QW3_NSR_I		PPC_BIT8(2)
 #define TM_QW3_NSR_GRP_LVL	PPC_BIT8(3,7)
 
+/* IVE/EAS */
+#define IVE_VALID		PPC_BIT(0)
+#define IVE_EQ_BLOCK		PPC_BITMASK(4, 7)	 /* Destination EQ block# */
+#define IVE_EQ_INDEX		PPC_BITMASK(8, 31)	 /* Destination EQ index */
+#define IVE_MASKED		PPC_BIT(32)		 /* Masked */
+#define IVE_EQ_DATA		PPC_BITMASK(33, 63)	 /* Data written to the EQ */
+
+/* EQ */
+#define EQ_W0_VALID		PPC_BIT32(0) /* "v" bit */
+#define EQ_W0_ENQUEUE		PPC_BIT32(1) /* "q" bit */
+#define EQ_W0_UCOND_NOTIFY	PPC_BIT32(2) /* "n" bit */
+#define EQ_W0_BACKLOG		PPC_BIT32(3) /* "b" bit */
+#define EQ_W0_PRECL_ESC_CTL	PPC_BIT32(4) /* "p" bit */
+#define EQ_W0_ESCALATE_CTL	PPC_BIT32(5) /* "e" bit */
+#define EQ_W0_UNCOND_ESCALATE	PPC_BIT32(6) /* "u" bit - DD2.0 */
+#define EQ_W0_SILENT_ESCALATE	PPC_BIT32(7) /* "s" bit - DD2.0 */
+#define EQ_W0_QSIZE		PPC_BITMASK32(12, 15)
+#define EQ_W0_SW0		PPC_BIT32(16)
+#define EQ_W0_FIRMWARE		EQ_W0_SW0 /* Owned by FW */
+#define EQ_QSIZE_4K		0
+#define EQ_QSIZE_64K		4
+#define EQ_W0_HWDEP		PPC_BITMASK32(24, 31)
+#define EQ_W1_ESn		PPC_BITMASK32(0, 1)
+#define EQ_W1_ESn_P		PPC_BIT32(0)
+#define EQ_W1_ESn_Q		PPC_BIT32(1)
+#define EQ_W1_ESe		PPC_BITMASK32(2, 3)
+#define EQ_W1_ESe_P		PPC_BIT32(2)
+#define EQ_W1_ESe_Q		PPC_BIT32(3)
+#define EQ_W1_GENERATION	PPC_BIT32(9)
+#define EQ_W1_PAGE_OFF		PPC_BITMASK32(10, 31)
+#define EQ_W2_MIGRATION_REG	PPC_BITMASK32(0, 3)
+#define EQ_W2_OP_DESC_HI	PPC_BITMASK32(4, 31)
+#define EQ_W3_OP_DESC_LO	PPC_BITMASK32(0, 31)
+#define EQ_W4_ESC_EQ_BLOCK	PPC_BITMASK32(4, 7)
+#define EQ_W4_ESC_EQ_INDEX	PPC_BITMASK32(8, 31)
+#define EQ_W5_ESC_EQ_DATA	PPC_BITMASK32(1, 31)
+#define EQ_W6_FORMAT_BIT	PPC_BIT32(8)
+#define EQ_W6_NVT_BLOCK		PPC_BITMASK32(9, 12)
+#define EQ_W6_NVT_INDEX		PPC_BITMASK32(13, 31)
+#define EQ_W7_F0_IGNORE		PPC_BIT32(0)
+#define EQ_W7_F0_BLK_GROUPING	PPC_BIT32(1)
+#define EQ_W7_F0_PRIORITY	PPC_BITMASK32(8, 15)
+#define EQ_W7_F1_WAKEZ		PPC_BIT32(0)
+#define EQ_W7_F1_LOG_SERVER_ID	PPC_BITMASK32(1, 31)
+
 /* Utilities to manipulate these (originaly from OPAL) */
 #define MASK_TO_LSH(m)		(__builtin_ffsl(m) - 1)
 #define GETFIELD(m, v)		(((v) & (m)) >> MASK_TO_LSH(m))