From patchwork Fri Apr 8 01:00:30 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 90242 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id E901AB6F85 for ; Fri, 8 Apr 2011 11:00:51 +1000 (EST) Received: (qmail 12133 invoked by alias); 8 Apr 2011 01:00:49 -0000 Received: (qmail 12121 invoked by uid 22791); 8 Apr 2011 01:00:47 -0000 X-SWARE-Spam-Status: No, hits=-1.4 required=5.0 tests=AWL, BAYES_00, NO_DNS_FOR_FROM, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mga09.intel.com (HELO mga09.intel.com) (134.134.136.24) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 08 Apr 2011 01:00:40 +0000 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 07 Apr 2011 18:00:39 -0700 X-ExtLoop1: 1 Received: from gnu-6.sc.intel.com ([10.3.194.135]) by orsmga001.jf.intel.com with ESMTP; 07 Apr 2011 18:00:31 -0700 Received: by gnu-6.sc.intel.com (Postfix, from userid 500) id C144F180DE0; Thu, 7 Apr 2011 18:00:30 -0700 (PDT) Date: Thu, 7 Apr 2011 18:00:30 -0700 From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Subject: [x32] PATCH: Add more x32 support to testsuite Message-ID: <20110408010030.GA18250@intel.com> Reply-To: "H.J. Lu" MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi, This patch has been in my tree for a couple weeks. I am checking it into x32 branch. H.J. diff --git a/gcc/testsuite/ChangeLog.x32 b/gcc/testsuite/ChangeLog.x32 index 9bcf223..0081f4c 100644 --- a/gcc/testsuite/ChangeLog.x32 +++ b/gcc/testsuite/ChangeLog.x32 @@ -1,3 +1,18 @@ +2011-03-16 H.J. Lu + + * g++.dg/opt/nrv12.C: Require ia32 instead of ilp32. + + * gcc.c-torture/compile/pr16566-2.c: Also allow x32. + * gcc.dg/torture/pr20314-2.c: Likewise. + * gfortran.dg/pr33794.f90: Likewise. + + * gcc.dg/lower-subreg-1.c: Don't allow x32. + + * gcc.dg/lto/pr47259_0.c: Don't require lp64. + + * gcc.dg/vect/costmodel/x86_64/x86_64-costmodel-vect.exp: Also + check x32. + 2011-03-15 H.J. Lu * lib/target-supports.exp (check_effective_target_vect_cmdline_needed): diff --git a/gcc/testsuite/g++.dg/opt/nrv12.C b/gcc/testsuite/g++.dg/opt/nrv12.C index 944dddd..ae09ca8 100644 --- a/gcc/testsuite/g++.dg/opt/nrv12.C +++ b/gcc/testsuite/g++.dg/opt/nrv12.C @@ -1,7 +1,7 @@ /* Verify that gimple-level NRV is occurring even for RESULT_DECLs. *./ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ /* { dg-options "-O -fdump-tree-optimized" } */ -/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target ia32 } */ struct P { diff --git a/gcc/testsuite/gcc.c-torture/compile/pr16566-2.c b/gcc/testsuite/gcc.c-torture/compile/pr16566-2.c index 2f7a106..72beb39 100644 --- a/gcc/testsuite/gcc.c-torture/compile/pr16566-2.c +++ b/gcc/testsuite/gcc.c-torture/compile/pr16566-2.c @@ -1,6 +1,6 @@ /* ICE with flexible arrays in non-lvalue structures. Bug 16566 (comment #5). */ -/* { dg-options "-Wno-psabi" { target { { i?86-*-* x86_64-*-* } && lp64 } } } */ +/* { dg-options "-Wno-psabi" { target { { i?86-*-* x86_64-*-* } && { x32 || lp64 } } } } */ struct A { diff --git a/gcc/testsuite/gcc.dg/lower-subreg-1.c b/gcc/testsuite/gcc.dg/lower-subreg-1.c index 4de90bd..3400c91 100644 --- a/gcc/testsuite/gcc.dg/lower-subreg-1.c +++ b/gcc/testsuite/gcc.dg/lower-subreg-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { { { ! mips64 } && { ! ia64-*-* } } && { ! spu-*-* } } } } */ +/* { dg-do compile { target { { { { ! mips64 } && { ! ia64-*-* } } && { ! spu-*-* } } && { ! x32 } } } } */ /* { dg-options "-O -fdump-rtl-subreg1" } */ /* { dg-require-effective-target ilp32 } */ diff --git a/gcc/testsuite/gcc.dg/lto/pr47259_0.c b/gcc/testsuite/gcc.dg/lto/pr47259_0.c index b959478..7900e5a 100644 --- a/gcc/testsuite/gcc.dg/lto/pr47259_0.c +++ b/gcc/testsuite/gcc.dg/lto/pr47259_0.c @@ -1,7 +1,6 @@ /* { dg-lto-do link } */ /* { dg-skip-if "" { ! { x86_64-*-* } } { "*" } { "" } } */ /* { dg-lto-options { { -O2 -flto -w } } } */ -/* { dg-require-effective-target lp64 } */ register int r asm("esi"); diff --git a/gcc/testsuite/gcc.dg/torture/pr20314-2.c b/gcc/testsuite/gcc.dg/torture/pr20314-2.c index 8185218..6da0983 100644 --- a/gcc/testsuite/gcc.dg/torture/pr20314-2.c +++ b/gcc/testsuite/gcc.dg/torture/pr20314-2.c @@ -1,5 +1,5 @@ /* PR inline-asm/20314 */ -/* { dg-do compile { target { { i?86-*-* x86_64-*-* } && lp64 } } } */ +/* { dg-do compile { target { { i?86-*-* x86_64-*-* } && { x32 || lp64 } } } } */ /* { dg-do compile { target ia64-*-* powerpc*-*-* } } */ int a, b, c, d, e, f, g, h, i, j, k, l; diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/x86_64/x86_64-costmodel-vect.exp b/gcc/testsuite/gcc.dg/vect/costmodel/x86_64/x86_64-costmodel-vect.exp index ff3650c..a11aa3b 100644 --- a/gcc/testsuite/gcc.dg/vect/costmodel/x86_64/x86_64-costmodel-vect.exp +++ b/gcc/testsuite/gcc.dg/vect/costmodel/x86_64/x86_64-costmodel-vect.exp @@ -22,7 +22,7 @@ load_lib gcc-dg.exp # Exit immediately if this isn't a x86 target. if { (![istarget x86_64-*-*] && ![istarget i?86-*-*]) - || ![is-effective-target lp64] } then { + || (![is-effective-target x32] && ![is-effective-target lp64]) } then { return } diff --git a/gcc/testsuite/gfortran.dg/pr33794.f90 b/gcc/testsuite/gfortran.dg/pr33794.f90 index a2425ce..80de044 100644 --- a/gcc/testsuite/gfortran.dg/pr33794.f90 +++ b/gcc/testsuite/gfortran.dg/pr33794.f90 @@ -1,5 +1,5 @@ ! { dg-do run } -! { dg-options "-O2 -ffast-math -mfpmath=387" { target { { i?86-*-* x86_64-*-* } && lp64 } } } +! { dg-options "-O2 -ffast-math -mfpmath=387" { target { { i?86-*-* x86_64-*-* } && { x32 || lp64 } } } } ! { dg-options "-O2 -ffast-math" } module scc_m